Table of Contents
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Revision
EVB
PCB Revision
A
ADC
B
REV 1.0
C
R301
+2V85_VRF_MTK
PCB_REVISION
1
2
1.0
100K
R1
1.1
R2
1.2
Seperate DC-DC GND to Main GND
VBATT
VBATT
P8
VBAT_SPK1
P7
VBAT_SPK2
P5
VBI_P
N5
VBI_N
N3
AUD1_P
N4
AUD1_N
P2
AUD2_P
P3
AUD2_N
C335
1u
M5
BYPASS
P13
SPK1_P
P12
SPK1_N
P10
SPK2_P
P11
SPK2_N
1%
R317
330k
N1
VCDT
VCHG_LDO_4V9
R318
3.3K
H5
CHR_LDO
L1
VDRV
1
1%
H1
C338
VBATT
ISENSE
H2
BATSNS
2.2u
K1
2
BATT_TEMP_ADC
BATON
J3
TREF
VTREF
M2
PCH_DET
K3
USB_DLN
L3
USB_DLP
A2
SRCLKENA
SRCLKEN
L2
AVDD18_DIG
RESET_IN
RESETB
N2
PWRKEY
PWR_ON_SW_N
M4
PMU_TESTMODE
M3
BBWAKEUP
PWRBB
B4
WATCHDOG_RESET
SYSRSTB
A4
FSOURCE
D3
SCL_2
SCK
D2
SDA_2
SDA
B3
INT
PMU_INT
C1
PMUCTRL0
DVS1
C4
PMUCTRL1
DVS2
B2
PACTRL0
PA_SEL0
C3
PACTRL1
PA_SEL1
B1
PA_SEL2
PACTRL2
A3
BL_PWM
E6
HOMEKEY
G1
CS+
G2
FGN_IC
CS-
K5
R321
1
2
32K_IN
100
RTCCLK_D
LGE Internal Use Only
R1
R2
ADC Value[V]
100K
5.6K
0.151136
100K
12K
0.305357
100K
19.1K
0.457053
100K
27K
0.605906
100K
47K
0.911224
100K
100K
1.425
100K
250K
2.035714
+1V8_VIO_MTK
AVDD18_DIG
2
2
2
2
2
2
2
2
2
2
C331
1
1
1
1
1
1
1
1
1
1u
1
F12
L301
2.2u
VCORE_1
F13
VCORE_2
E12
VCORE_3
C332
4.7u
B12
VCORE_FB
C14
L302
2.2u
VPROC_1
D13
C333
4.7u
VPROC_2
D14
VPROC_3
C334
10n
E10
VPROC_FB
VAPROC_FB
G12
L303
2.2u
VIO18_1
G13
VIO18_2
C336
4.7u
D301
A13
1
2
VIO18_FB
J13
L304
4.7u
VPA_1
K13
VPA_2
2
C12
C337
VPA_FB
2.2u
L305
2.2u
H12
1
1
U804
VRF18
+1V8_VRF_MTK
2
C339
4.7u
D12
VRF18_FB
FOR PI TEST
A10
R320
0
1.2V,300mA
VM12_1
1
2
C9
0.9-1.2V,300mA
VM12_2
B10
1.2V,360mA
VM12_INT
E1
2.85V,200mA
VRF28
F5
2.8V,40mA
VTCXO
E3
1.8-2.5V,100mA
VA1
B9
2.8V,100mA
VIO28
A8
1.8/3.0V,100mA
VSIM
C8
1.3-3.3V,100mA
VSIM2
C10
1.3-3.3V,200mA
VMC
A11
1.3-3.3V,400mA
VMCH
B7
1.3-3.3V,200mA
VGP
B11
1.3-3.3V,100mA
VGP2
B8
3.3V,100mA
VUSB
F2
1.5-2.8V,200mA
VCAMA
F3
VCAMA_S
A7
1.3-3.3V,200mA
VCAM_AF
B5
1.3-3.3V,300mA
VCAMD
A5
1.3-3.3V,100mA
VCAM_IO
B6
1.3-3.3V,100mA
VIBR
G3
2.5/2.8V,100mA
VA2
G5
VA2_BUF
E7
1.8-2.8V,2mA
VRTC
J2
C340
1u
VRET
2
K2
C342
GND_VREF
1u
1
J5
CHG_DP
CHD_DP
H3
CHG_DM
CHD_DM
[8GB eMMC_8Gb LPDDR2] FOR V5
+1V8_VIO_MTK
C1
eMMC_RST
B5
R305
eMMC_CLK
1
2
C5
27
eMMC_CMD
R306
+1V8_VIO_MTK
2
1
F7
+1V2_VLPDDR2_MTK
10K
F10
2
2
2
G5
H9
J10
1
1
1
L6
M6
N6
R10
T9
U5
V7
V10
A5
B8
+1V8_VIO_MTK
A8
+3V3_eMMC_MTK
2
B2
C306
2
2
2
C3
1u
C311
1
1u
1
1
B9
1
E1
TP301
T8
DDRAM_DATA_[0]
1
R8
DDRAM_DATA_[1]
R7
DDRAM_DATA_[2]
R9
DDRAM_DATA_[3]
R6
DDRAM_DATA_[4]
P7
DDRAM_DATA_[5]
P8
DDRAM_DATA_[6]
P9
DDRAM_DATA_[7]
K9
DDRAM_DATA_[8]
K8
DDRAM_DATA_[9]
K7
DDRAM_DATA_[10]
J6
DDRAM_DATA_[11]
J9
DDRAM_DATA_[12]
J7
DDRAM_DATA_[13]
J8
DDRAM_DATA_[14]
H8
DDRAM_DATA_[15]
W7
DDRAM_DATA_[16]
U6
DDRAM_DATA_[17]
W8
DDRAM_DATA_[18]
T5
DDRAM_DATA_[19]
U7
DDRAM_DATA_[20]
W9
DDRAM_DATA_[21]
V8
DDRAM_DATA_[22]
T6
DDRAM_DATA_[23]
H6
DDRAM_DATA_[24]
F8
DDRAM_DATA_[25]
E9
DDRAM_DATA_[26]
G7
DDRAM_DATA_[27]
H5
DDRAM_DATA_[28]
E8
DDRAM_DATA_[29]
G6
DDRAM_DATA_[30]
E7
DDRAM_DATA_[31]
N5
DDRAM_DQM_[0]
L5
DDRAM_DQM_[1]
T7
DDRAM_DQM_[2]
H7
DDRAM_DQM_[3]
K3
+0V6_VREF
M9
P1
DDRAM_CS_[0]_N
P2
DDRAM_CS_[1]_N
N1
DDRAM_CLK_EN
N2
G3
2
2
C318
1u
1
1
+1V2_CORE_MTK
+1V35_PROC_MTK
+1V8_VIO_MTK
VBATT
+3V4_VWPAM_MTK
+1V2_VLPDDR2_MTK
+1V2_VM12_INT_MTK
+2V85_VRF_MTK
+2V8_VTCXO_MTK
+2V5_AVDD1_MTK
+2V8_VIO_MTK
+3V0_VSIM_MTK
+3V0_VSIM2_MTK
+3V3_eMMC_MTK
+3V3_MICRO_SD
+3V3_MICRO_IO
+3V0_TOUCH_MTK
+3V3_USB_MTK
+3V0_SENSORS_MTK
+3V0_LCD_VCI_MTK
+1V8_LCD_VIO_MTK
+3V0_VIBR_MTK
+2V5_AVDD2_MTK
+2V8_VRTC_MTK
- 154 -
P5
RST
DQS0_C
DDRAM_DQS_[0]_N
K5
DQS1_C
DDRAM_DQS_[1]_N
U9
CLKM
DQS2_C
DDRAM_DQS_[2]_N
G9
DDRAM_DQS_[3]_N
CMD
DQS3_C
P6
DQS0_T
DDRAM_DQS_[0]_P
K6
VDDQ1
DQS1_T
DDRAM_DQS_[1]_P
U8
VDDQ2
DQS2_T
DDRAM_DQS_[2]_P
G8
VDDQ3
DQS3_T
DDRAM_DQS_[3]_P
VDDQ4
L3
VDDQ5
CLK_C
DDRAM_CLK_N
M3
VDDQ6
CLK_T
DDRAM_CLK_P
VDDQ7
F6
VDDQ8
VSSQ1
F9
VDDQ9
VSSQ2
G10
VDDQ10
VSSQ3
H10
VDDQ11
VSSQ4
J5
VDDQ12
VSSQ5
K10
VDDQ13
VSSQ6
M5
VSSQ7
P10
VDDI
VSSQ8
R5
VSSQ9
T10
VCCQ
VSSQ10
U10
VSSQ11
V6
VCC1
VSSQ12
V9
VCC2
VSSQ13
A3
VSSQM
DAT0
B3
DAT1
B7
VSSM1
DAT2
A7
VSSM2
DAT3
B6
DAT4
A6
DQ0
DAT5
A4
DQ1
DAT6
B4
DQ2
DAT7
DQ3
E6
DQ4
VDD1_1
+1V8_VIO_MTK
F1
DQ5
VDD1_2
U301
V1
DQ6
VDD1_3
W6
DQ7
VDD1_4
DQ8
E5
DQ9
VDD2_1
+1V2_VLPDDR2_MTK
G2
DQ10
VDD2_2
K1
2
2
2
DQ11
VDD2_3
M7
DQ12
VDD2_4
U2
DQ13
VDD2_5
1
1
1
W5
DQ14
VDD2_6
DQ15
F2
DQ16
VSS1
F5
2
2
DQ17
VSS2
G1
DQ18
VSS3
M8
DQ19
VSS4
U1
1
1
DQ20
VSS5
V2
DQ21
VSS6
V5
DQ22
VSS7
L2
DQ23
VSS8
DQ24
J1
DQ25
VDDCA1
L1
DQ26
VDDCA2
T2
DQ27
VDDCA3
DQ28
H1
DQ29
VSSCA1
M1
DQ30
VSSCA2
T1
DQ31
VSSCA3
DM0
U3
DM1
CA0
DDRAM_ADDRESS_[0]
T3
DM2
CA1
DDRAM_ADDRESS_[1]
R3
DM3
CA2
DDRAM_ADDRESS_[2]
R2
CA3
DDRAM_ADDRESS_[3]
R1
VREFCA
CA4
DDRAM_ADDRESS_[4]
K2
VREFDQ
CA5
DDRAM_ADDRESS_[5]
J2
CA6
DDRAM_ADDRESS_[6]
J3
CS0_N
CA7
DDRAM_ADDRESS_[7]
H3
CS1_N
CA8
DDRAM_ADDRESS_[8]
H2
CKE0
CA9
DDRAM_ADDRESS_[9]
CKE1
ZQ
Copyright © 2013 LG Electronics. Inc. All right reserved.
6. CIRCUIT DIAGRAM
+1V2_VLPDDR2_MTK
2
1
+0V6_VREF
2
1
+1V8_VIO_MTK
eMMC_DATA[0]
eMMC_DATA[1]
eMMC_DATA[2]
eMMC_DATA[3]
eMMC_DATA[4]
eMMC_DATA[5]
eMMC_DATA[6]
eMMC_DATA[7]
Only for training and service purposes
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Troubleshooting
