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Schematic and Bill of Materials
7
Schematic and Bill of Materials
This section contains the DRV10983 schematic and bill of materials (BOM).
7.1
Schematic
Figure 22
shows the DRV10963 motherboard schematic.
Interface Connectors for Daughter Board
P1
1
VCC
1
2
VCC
2
FR
3
3
PWM
U
4
4
FGS
U
5
5
FG
W
6
6
TOSC
W
7
7
V
8
8
V
9
9
GND
10
10
GND
11
11
P3
1
2
3
4
PowerIn
TP6
1
3
S1
PowerIn plus test mode entry
voltage Power
TP8
TP9
To Enable OTP programming Test Voltage
V_TESTMODE
R4
10.0k
1
R5
1.00k
V3P3
Q1
R6
Q2
10.0k
R7
4.7k
20
DRV10963 Evaluation Module
P2
TP2
TP1
TP3
U
W
V
SCLK
V TestMode= 6.2Volt
Vcc=5Volt
V_TESTMODE
VCC
U1
TP7
VCC
TP4
1
VI
C4
C1
10µF
4.7µF
3
EN
C5
C2
47µF
10µF
TPS62203DBV
2
V_TESTMODE
V3P3
VCC
R1
R3
R2
1.00k
3.01k
3.01k
C6
0.1µF
LED1
LED2
GND
TP11
TP12
TP13 TP14
Test Points for GND
For Factory Testing
V3P3
J1
R8
10.0k
R11
TOSC
1.00k
R13
Q3
FGS_CNTL
Q4
10.0k
R14
4.7k
Figure 22. DRV10963 Motherboard Schematic
Copyright © 2015, Texas Instruments Incorporated
USB to Any Connector
P4
1
2
3
4
5
6
FGS_CNTL
7
8
SDATA
9
10
GND
5103308-1
C8
0.01µF
L1
V3P3
5
SW
10µH
V3P3
4
FB
C3
10µF
2
GND
LED3
J3
FGS
Speed Control Section
555 Timer as PWM Generator ~25kHz
R16
VCC
10.0k
U4
PWM_Duty
4
7
RST
DIS
6
3
THR
OUT
2
5
TRIG
CVOLT
C7
8
1
+VCC
GND
0.01µF
TLC555
D1
D2
C9
0.1µF
R17
5K
I2C Communication
V3P3
R9
4.7k
S2
1
R12
2
PWM
100
SCLK
3
PWM_Duty
S2-1: I2C communication with GUI
S2-3:
PWM duty cycle for speed control using POT
V3P3
R10
U2
4.7k
FR_BUF
Must have a single point for bidirectional
FR_BUF
4
2
MBRM110L
R15
SDATA
FR
100
TP16
U3
FG_BUF
J2
FG
4
2
FG_BUF
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SLAU643 – July 2015
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