Fostex D-108 Service Manual page 48

GATE ARRAY, MAIN, D-108 (4/11)
J9
1
2 /OP_RST
3 OP_D0
4 OP_D1
5 OP_D2
6 OP_D3
7 OP_D4
8 OP_D5
9 OP_D6
10 OP_D7
11 OP_A1
12 OP_A2
13 OP_A3
14 OP_A4
15 OP_A5
16 /OP_IRQ
17 /OP_WR
18 /OP_RD
19 /CS_OP1
20 /CS_OP2
21 /CS_OP3
22 /CS_OP4
23 /LRCK /CS_OP[1..4]
24 EXT_LRCK
25 D+5
0.01
FC 25P
C21
10/16
DGND
DGND
SCSI
/ATA_RST
/ATA_RST /ATA_RST
DD[0..17]
DD[0..17] DD[0..17]
D+5
R95
R96
1K
1K
DMARQ
DMARQ DMARQ
/DIOW
/DIOW /DIOW
/DIOR
/DIOR /DIOR
IORDY_I
IORDY_I IORDY_I
/DMACK
/DMACK /DMACK
/PDIAG
/PDIAG /PDIAG
INTRQ
INTRQ INTRQ
/CS1FX
/CS1FX /CS1FX
/CS3FX
/CS3FX /CS3FX
R9
5.6K
R8
10K
DGND
ATA[0..4]
ATA[0..4] ATA[0..4]
/DMA_RD
/DMA_RD /DMA_RD
/DMA_WR
/DMA_WR /DMA_WR
/SCSI_CS
/SCSI_CS /SCSI_CS
DMA_SEL
DMA_SEL DMA_SEL
/SCSI_DREQ
/SCSI_DREQ /SCSI_DREQ
C29
(CHIP C)
SC_INT7I
SC_INT7I SC_INT7I
SCSI_TMOUT SCSI_TMOUT
28MHZ
28MHz 28MHz
D+5
D+5
D+5 D+5
GND
DGND DGND
SCSI.SCH DGND
DGND
U6E
11 10
74HCU04
DGND
OP_A[1..5]
OP_D[0..7]
D+5 D+5
C90 C89
0.01 0.01
U18
DGND DGND
74HC245
DGND
/OP_IRQ
C24
C22
0.01
C23 C25
0.01 0.01
37
NC
38
VSS
39
ATA_RES
DD7 40
ATA_D7
DD8 41
ATA_D8
DD6 42
ATA_D6
DD9 43
ATA_D9
44
VSS
DD5 45
ATA_D5
DD10 46
ATA_D10
DD4 47
ATA_D4
DD11 48
ATA_D11
DD3 49
ATA_D3
DD12 50
U5
ATA_D12
DD2 51 GA2
ATA_D2
DD13 52
ATA_D13
DD1 53
ATA_D1
54
VDD
55
VDD
DD14 56
ATA_D14
DD0 57
ATA_D0
DD15 58
ATA_D15
59
DMARQ
60
DIOW
61
DIOR
62
IORDY_I
63
DMACK
64
VSS
65
VSS
66
INTRQ
67
ATA_A1
68
ATA_A0
69
ATA_A2
70
CS1FX
71
VSS
72
VDD
C30
470P
SCSI_CS
DMA_SEL
R12
ATA3
100
ATA4
SC_INT7I R97
CPU
SCSI_TMOUT
1M
28MHZ
12 13 U6F
74HCU04 R14
C28
W2 X4
100p
(CHIP R) (XTAL) 20MHz
C910 C911
(CHIP C) 0 6
DGND
74HCU04
R15
0
U6B
R91
4 3
100 C31
74HCU04 22P
DGND
D+5 VCO+5
POWER
D+5 VCO+5
POWER
DGND VCOGND
DGND GND VCOGND
U34C
9
/CS_OP[1..4] 8
10
non
U34D
12
11
13
non
U17
DGND
74HC541
U16A
/CS_OP1 4 2
Y0 A
/CS_OP2 5 3
Y1 B
/CS_OP3 6
Y2
/CS_OP4 7 1
Y3 G
16
VCC
74HC139
/CS_OP
C912
33p R902 560
MSCK_ADDA
R55
MSCK_AD
ADDA
560
R56
144
VDD BCK_ADDA
143
560
VSS R57
142
WR LRCK
141
100
RD
140
NC
139
ATA_INT /ATA_INT1
138 100
MLRCK /AIRQ1 TDO_FS1O
137 CPU 99
DACK_I /DACK1 W_OUT
136 98
VSS W_IN2
135 97
ATA_DREQ /DREQ1 W_IN1
134 96
RST 256FSO
133 95
SLAVE VARI/EXT BCKO
132 C27 94
TCRC LRCKO
131 470p 93
TST2 LRCKI
130 92
TCK2 BCKI
129 DGND 91
VDD VDD
128 90
DIGITAL_OUT_2 VSS
127 89
DIGITAL_IN_2 FS256I
126 88
DIGITAL_OUT_1 PCMBW0
125 87
DIGITAL_IN_1 PCMBW1
124 86
TEST CK_SEL0
123 VCO 85
EXT_MCLK2 CK_SEL1
122 84
FCONT2 VARI/EXT VARI/EXT CK_SEL2
121 83
PD2 PLL2_CONT PLL2_CONT PLL2_CONT
120 82
PLL_SEL LOCK2B
119 81
FCONT1 FCONT2 FCONT2 FCONT2
118
PD1 /LOCK2B /LOCK2B
117
EXT_MCLK1
116 TP9
VSS
115 TP
VDD
114 VARI_256FS
VARI_256FS VARI_256FS VARI_256FS
113 VARI_FS
VARI_FS VARI_FS VARI_FS
112 S_MSCK
SLAVE_MSCK
111 PD2
SLAVE_MLRCK PD2 PD2
110
NC
109
NC
MCK2
MCK2 MCK2
MLRCK MLRCK PLL1_CONT PLL1_CONT
FCONT1 FCONT1
PD1
PD1 PD1
MCK1
EXT_LRCK EXT_LRCK MCK1 MCK1
ADAT_IN ADAT_IN
vco.sch
R1
2 1 DA2_D1
4 3 DA2_D2 SOUT[1..5]
6 5 DA2_D3
8 7 DA2_D4
W12
100x4 R89 DA2_D5
SOUT5
100 NON
SOUT4 D+5
SOUT3 R99
SOUT2 330
R6
C98
SOUT1
100 0.01
DGND
4 3
R5 R13
R17 6
100 330
1M 1M
5
U4A
U4B 74HC00
74HC00 U4D
U6D 12
5 8 9 74HCU04 11
13
U4C
U6C
74HC00
8
R18
74HC00
0
X1 X2
22.5792MHz 24.576MHz
C32 C35 C36
22P 22P 22P
DA_D[1..4]
DGND
D+5
C920
non
U34B
R922
5 DGND
6
1M
4
non
R921
1
3
non
C921
2
D+5 non
U34A
non
C87
DGND
0.01
U16B
DGND /CS_GA 12 14
Y0 A
11 13
Y1 B
/CS_DIG 10
Y2
9 15 /CS1
Y3 G /CS1
W14 74HC139
0
D[0..15]
D[0..15]
A[0..18]
A[0..18]
/CS_IDE
/CS_IDE
IORDY1
IORDY1
/WR
/RD
/RST
C919
470P
U20
31
SOUT1_MD
32
SOUT2_MD
33
TDI_FS1I
34
TDI_FS0I
35
TDI_EMPI
36 AD_D1
SINA_12
37 AD_D2
SINA_34
38 AD_D3
SINA_56
39 AD_D4
SINA_78
40
VSS
41
VDD
42 DA2_D1 AD_D[1..4]
SINB_12
43 DA2_D2
SINB_34
44 DA2_D3
SINB_56
45 DA2_D4
SINB_78
46 DA2_D5
SIN_DIF
47
DI1
48
DI2
49
DI_SEL
50
DI_FS1O
DIFGA
C83 C84
0.01 0.01
TP10
TP
R7
100
DA2_D[1..5]
R84
100
SOUT5 D+5
D+5
SOUT4 8 7 C26
10/16
SOUT3 6 5
SOUT2 4 3 J5
SOUT1 2 1 C33 1
R10
0.01
3.3K
3
R2
R16
100x4 2
R11
330
2.2K
1 GPIF32R
2 DATA IN(OPT)
DGND
D+5
J4
C20 2
D+5 0.01
9 1
10 R3 3
DA_D1 8 7 DA2_D1
DA_D2 6 5 DA2_D2 DGND GPIF32T
DA_D3 4 3 DA2_D3
DA_D4 2 1 DA2_D4 DATA OUT(OPT)
100x4
DA_D[1..4]
CPU
CPU
CPU
/WR
CPU
/RD
/RST
AD_D[1..4]
D+5
C85 C86
DGND
0.01 0.01
4
5
6
4
5
6