Advertisement
TH-A5R
2. Pin function
Name
SDDATA[7]/VDATA2[7]
/HDMARQ/GPIO24
SDDATA6/VDATA2[6]
/HXCVR_EN/GPIO25
SDDATA5/VDATA2[5]
HDMACK/GPIO26
SDDATA4/VDATA2[4]/
GPIO27
SDDATA3/
VDATA2[3]/GPIO28
SDDATA2/
VDATA2[2]/GPIO29
SDDATA1/
VDATA2[1]/GPIO30
SDDATA0/
VDATA2[0]/GPIO31
SDCLK
SDERROR
SDEN/GPIO33
SDREQ/GPIO32
VDAC_[4B:0B]
VDAC_4
VDAC_3V
DAC_2
VDAC_1
VDAC_0
VDAC_REF
VCLK
ADATA[3:0]/GPIO[4:1]
BCK
LRCK
XCK
IEC958/GPIO14
DAI_DATA/GPIO15
DAI_BCK/
BYPASS_SYSCLK/
GPIO16
DAI_LRCK/
IEC958BP/GPIO17
1. I - input, O - output, OD - open drain, PU - requires external pull-up resistor.
1-18
Pin No.
Type
168
169
170
171
174
175
176
177
183
182
179
178
117, 120, 123, 126, 129
Analog O
119
Analog O
122
Analog O
125
Analog O
128
Analog O
131
Analog O
135
Analog I
105
I/O
155, 154, 151, 150
149
148
147
I/O
156
157
158
159
1
Description
I
Compressed data from DVD DSP. Bit 7. In parallel mode, bit 7 is the first
(earliest in time) bit in the bitstream, while bit 0 is the last bit.
Video Data Bus 2, Bit 7
Host DMA Request
General Purpose I/O 24
Compressed data from DVD DSP. Bit 6.
Video Data Bus 2, Bit 6
ATAPI Transceiver Enable
General Purpose I/O 25
Compressed data from DVD DSP. Bit 5.
Video Data Bus 2, Bit 5
Host DMA Acknowledge
General Purpose I/O 26
Compressed data from DVD DSP. Bit 4.
Video Data Bus 2, Bit 4
General Purpose I/O 27
Compressed data from DVD DSP. Bit 3.
Video Data Bus 2, Bit 3
General Purpose I/O 28
Compressed data from DVD DSP. Bit 2.
Video Data Bus 2, Bit 2
General Purpose I/O 29
Compressed data from DVD DSP. Bit 1.
Video Data Bus 2, Bit 1
General Purpose I/O 30
In serial mode, bit 0 should be used as the input, with the unused bits
either used as GPIOs or tied to ground.
Video Data Bus 2, Bit 0
General Purpose I/O 31
I
Data clock. The maximum frequency is 25 MHz for parallel mode, and
???? MHz for serial mode. The polarity of this signal is programmable.
I
Error in input data. This signal carries the error bit associated with the
channel data type (if set, the byte is ccorrupted).
I
Data enable. Assertion indicates that data on SDDATA[7:0] is valid.
The polarity ofthis signal is programmable.
General Purpose I/O [33]
O
Bitstream request. controller asserts SDREQ to indicate that the bitstream
input buffer has available space.
General Purpose I/O 32
Video DAC Bias Bits[4:0]
DAC video output format: R, V, C, or CVBS. Macrovision encoded.
DAC video output format: B, U, C, or CVBS. Macrovision encoded.
DAC video output format: G or Y. Macrovision encoded.
DAC video output format: C. Macrovision encoded.
DAC video output format: CVBS or Y. Macrovision encoded.
Video DACs Reference Resistor. Connecting to pin 136 through
a 1.18K+/- 1% resis-tor is required.
System clock that drives internal PLLs. ZiVA-5 27-MHz TTL oscillator.
(See descrip-tion of VCLK for Digital Video Output.) Also optional video
clock for internal PLLs or external encoder.
O
PCM Data Out. Eight channels. Serial audio samples relative to BCK
and LRCK. General Purpose I/Os [4:1]
O
PCM Bit Clock. BCK can be either 48 or 32 times the sampling frequency
PCM Left Clock. Identifies the channel for each sample. The polarity is
O
programma-ble.
Audio External Frequency clock input or output. BCK and LRCK are
derived from this clock.
O
PCM data out (IEC-958 format ) or compressed data out
(IEC-1937 format). General Purpose I/O [14]
I
PCM data input.
General Purpose I/O [15]
I
PCM input bit clock.
BYPASS_SYSCLK: Alternate function TBS.
General Purpose I/O [16]
I
PCM left/right clock.
IEC958 input bypass
General Purpose I/O [17]
(3/4)
Advertisement
