LG -P768 Service Manual page 147

Boot Configuration
MODE DSP_AUDIO_IN1 MON1 MON2 IFX_TRIG_IN
1 0 0 0 1
2 0 0 1 0
0
5 1 0 1
6 0 1 1 0
9 1 0 0 1
11 1 0 1 1
1 1 0 0
12
14
1 1 1 0
Boot Configuration
VSD2_1.8V
R401 R402
4.7K 4.7K
DSP_AUDIO_IN1
MON1
MON2
IFX_TRIG_IN
R403 R404
4.7K 4.7K
MEM_WP/
MEM_BUSY/
MEM_CS0_N
MEM_CS1_N
MEM_ADV_N
MEM_RD_N
MEM_WR_N
MEM_WAIT_N
DDR_RAS_N
DDR_CAS_N
MEM_BC0_N
MEM_BC1_N
DDR_DQS[0]
DDR_DQS[1]
MEM_SDCLKO
MEM_BFCLKO
VSD1_1.3V
CP_DOWN_CHECK
C423 C424 C425 C426
0.1u 0.22u 0.1u 0.22u
VSD2_1.8V
VSIM_2.9V
VUSB_IO_3.1V
VSD2_1.8V
VPLL_1.2V
VIO_1.2V
VUSB_PD_1.1V R411 4.7
VUSB_ANA_1.8V
C437
C430 C431 C432 C433 C434 C435 C436
EXXY0026801
0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u
0.1u 32.768KHz
NIHON-DEMPA
revA(10pF) -> revB(22pF)
LGE Internal Use Only
BASE BAND PROCESSOR
IFX_TRIG_IN
16bit AD NOR
16bit AAD NOR
8bit NAND
16bit NAND
eMMC
16bit SDRAM
shared2
16bit SDRAM
shared1
Flashless boot
VBAT
TP413 TP414
FB401 FB402
VBAT
BLM15PD600SN1D
C414
10u
C415 C416
VSD2_1.8V
10u 10u
VSD1_1.3V
L401 3.3u
L402 3.3u
C418
TP410
22u
C419
22u
VSD2_1.8V
R408
R409
DNI 4.7K
B8
FWP
A6
FCDP_RBn
J14
MEM_CS0_N
J13
MEM_CS1_N
H14
MEM_CS2_N
H13
MEM_CS3_N
G10
MEM_ADV_N
B13
MEM_RD_N
B12
MEM_WR_N
K17
MEM_WAIT_N
E14
MEM_RAS_N
B7
MEM_CAS_N
G14
MEM_BE0_N
G13
MEM_BE1_N
A12
MEM_BC0_N
F16
MEM_BC1_N
B10
MEM_BC2_N
G16
MEM_BC3_N
A14
MEM_SDCLKO
B15
MEM_BFCLKO_0
A15
MEM_BFCLKO_1
B14
DDR_CKE MEM_CKE
L7
MMCI1_CMD
M3 U402
MMCI1_CLK
M5
MMCI_DAT_0
M2
MMCI1_DAT_1
M4
MMCI1_DAT_2
M6
MMCI1_DAT_3
XMM6260
N5
IFX_RTCK MMCI1_CD
K14
VDD_CORE_1
H9
VDD_CORE_2
E10
VDD_CORE_3
E13
VDD_CORE_4
EUSY0432001
K9
VDD_CORE_3G_1
R8
VDD_CORE_3G_2
E12
VDD_CORE_EBU
K8
VDD_IO18_1
B11
VDD_IO18_2
F15
FL401 NFM15PC105R0J3D VDD_IO18_3
N11
VDD_IO18_4
IN OUT
K11
GND1 GND2 VDD_IO18_5
J17
VDD_IO18_6
EAM62451701
L8
VDD_MMC
T12
VDD_SIM
R16
VDD_USBIO
K16
VDD_MIPI
R12
VDD_PLL
U15
VDD_IO12
N9
VPP
T15
VDD_USB_PD
P14
VDD_USB_ANA
T10
VDD_DIGRF
L17
C438 22p
F32K
M17
OSC32K
M16
VSS_RTC
N17
NX3215SA VDD_RTC
C439 22p
VRTC_1.8V
C440 C441
220n 10u
DI3_RX_DAT
R417 R417 must be close to U402(Baseband)
100
DI3_RX_DATX
DI3_TX_DAT
DI3_TX_DATX
DI3_SYS_CLK
DI3_SYS_CLK_EN
RESET_N
DI3_REF_CLK_EN
TP401 TP402
TP403 TP404
IPC_I2S_CLK
TP405
IPC_I2S_DIN
TP408
IPC_I2S_DOUT
TP409
IPC_I2S_SYNC
CP_CRASH_INT
TP412
M9
EINT1 IPC_SRDY
M8
EINT2 IPC_MRDY
K10
OMAP_SEND
EINT3
N10
I2C1_SCL
P9
I2C1_SDA
B6
DSP_AUDIO_IN1 DSP_AUDIO_IN1
N8
CLKOUT0 26MHz_GPS_REF
P10
CLKOUT2
N4
T_OUT0 MODEM_SEND
P3
T_OUT1
GSM_TXON_IND
R5
RESET2_N
N13
MIPI_HSI_RX_DATA MIPI_HSI_AC_DATA
M14
MIPI_HSI_RX_FLG MIPI_HSI_AC_FLAG
L13
MIPI_HSI_RX_RDY MIPI_HSI_CA_READY
P13
MIPI_HSI_RX_WAKE MIPI_HSI_AC_WAKE
N12
MIPI_HSI_TX_DATA MIPI_HSI_CA_DATA
L11
MIPI_HSI_TX_FLG MIPI_HSI_CA_FLAG
M15
MIPI_HSI_TX_RDY MIPI_HSI_AC_READY
M13
MIPI_HSI_TX_WAKE MIPI_HSI_CA_WAKE
A13
MEM_A_0 MEM_A[0]
A11
MEM_A_1 MEM_A[1]
A10
MEM_A_2 MEM_A[2]
A9
MEM_A_3 MEM_A[3]
A8
MEM_A_4 MEM_A[4]
C12
MEM_A_5 MEM_A[5]
B9
MEM_A_6 MEM_A[6]
C9
MEM_A_7 MEM_A[7]
A16
MEM_A_8 MEM_A[8]
B17
MEM_A_9 MEM_A[9]
C17
MEM_A_10 MEM_A[10]
D17
MEM_A_11 MEM_A[11]
E17
MEM_A_12 MEM_A[12]
F17
MEM_A_13 MEM_A[13]
G17
MEM_A_14 MEM_A[14]
H17
MEM_A_15 MEM_A[15]
J16
MEM_A_16
H16
MEM_A_17
J15
MEM_A_18
G15
MEM_A_19
E16
MEM_A_20
D16
MEM_A_21
C16
MEM_A_22
B16
MEM_A_23
H11
MEM_AD[0]
MEM_AD_0
G11
MEM_AD_1 MEM_AD[1]
G9
MEM_AD[2]
MEM_AD_2
D8
MEM_AD_3 MEM_AD[3]
F9
MEM_AD_4 MEM_AD[4]
E8
MEM_AD_5 MEM_AD[5]
E9
MEM_AD_6 MEM_AD[6]
D10
MEM_AD_7 MEM_AD[7]
E11
MEM_AD_8 MEM_AD[8]
A7
MEM_AD_9 MEM_AD[9]
H10
MEM_AD_10 MEM_AD[10]
D11
MEM_AD_11 MEM_AD[11]
D12
MEM_AD_12 MEM_AD[12]
D13
MEM_AD_13 MEM_AD[13]
J12
MEM_AD_14 MEM_AD[14]
F13
MEM_AD_15 MEM_AD[15]
IFX_USB_VBUS_EN
(Active high)
- 147 -
NAND MCP
VSD2_1.8V
U401
H9DA1GH25HAMMR-4EM
A8 J4
VDD1 A0
C1 K1
FL400
VDD2 A1
NFM18PS105R0J3D_
G1 K2
C401 VDD3 A2
IN OUT G10 K3
2.2u VDD5 A3
GND L1 B2
VDD4 A4
N8 C2
VDD6 A5
D1
A6
B9 C3
VDDQ1 A7
C10 D2
VDDQ6 A8
D9 C4
VDDQ5 A9
E10 J3
VDDQ4 A10
F9 E2
VDDQ10 A11
H10 E1
VDDQ9 A12
J9 H3
VDDQ2 BA0
K9 J2
VDDQ8 BA1
L10
VDDQ7
M9 K4
VDDQ3 DQ0
K5
DQ1
K6
DQ2
A2 K7
NC27 DQ3
D4 J8
NC20 DQ4
D6 K8
NC21 DQ5
E3 J7
NC9 DQ6
E4 J5
NC19 DQ7
E5 E6
NC8 DQ8
E7 C5
NC11 DQ9
E8 D8
NC12 DQ10
F1 C6
NC17 DQ11
F3 C8
NC18 DQ12
F4 C7
NC7 DQ13
F5 B8
NC16 DQ14
F6 B7
NC25 DQ15
F7
NC6
G3 G8
NC10 CLK#
G4 F8
NC5 CLK
G5 D3
NC13 CKE
G6 H2
NC14 CS#
G7 F2
NC4 RAS#
H4 G2
NC2 CAS#
H5 J1
NC24 WE#
H6 D7
NC22 UDQM
J6 H8
NC23 LDQM
L3 D5
NC15 UDQS
L4 H7
NC3 LDQS
VSD2_1.8V
A5 M1
VCC1 IO0
M5
M2
VCC2 IO1
M3
C422
C420 C421 IO2
L5
2.2u IO3
0.1u 0.1u
N7
IO4
L6
IO5
A9 M6
VSS1 IO6
B1 L8
VSS4 IO7
B5 N2
VSSn2 IO8
B10 N3
VSSQ5 IO9
C9 M4
VSSQ4 IO10
D10 N4
VSSQ9 IO11
E9 N5
VSSQ8 IO12
F10 M7
VSSQ3 IO13
G9 L7
VSS2 IO14
H1 M8
VSS3 IO15
H9
VSSQ10
J10 A6
VSSQ1 CE#
K10 A3
VSSQ2 RE#
L2 A7
VSS5 WEn#
L9 A4
VSSQ6 CLE
M10 B4
VSSQ7 ALE
N6 B3
VSSn1 WP#
N9 B6
VSS7 R/B#
EAN62327101
Analog switch for USIF1
USB_VBUS
IFX_USB_VBUS
VBAT
R415
100K
Q401 SSM6L39TU
1 6
1
S1 D1
VCC
UART_RX_SW 2
1B1
2 5
G1 G2
3 4
C442
D2 S2
R416 100n
4.7K EBK61693301
S1,S2 UART_RX_IFX(1A) UART_TX_IFX(2A)
0
UART1_TX_IPC(1B0) UART1_RX_IPC(2B0)
1 UART_RX_SW(1B1) UART_TX_SW(2B1)
Copyright © 2012 LG Electronics. Inc. All right reserved.
7. CIRCUIT DIAGRAM
MEM_AD[0]
MEM_AD[1]
MEM_AD[2]
MEM_AD[3]
MEM_AD[4]
MEM_AD[5]
MEM_AD[6]
MEM_AD[7]
MEM_AD[8]
MEM_AD[9]
MEM_AD[10]
MEM_AD[11]
MEM_AD[12]
MEM_AD[14]
MEM_AD[15]
MEM_A[0]
MEM_A[1]
MEM_A[2]
MEM_A[3]
MEM_A[4]
MEM_A[5]
MEM_A[6]
MEM_A[7]
MEM_A[8]
MEM_A[9]
MEM_A[10]
MEM_A[11]
MEM_A[12]
MEM_A[13]
MEM_A[14]
MEM_A[15]
MEM_BFCLKO
MEM_SDCLKO
DDR_CKE
MEM_CS1_N
DDR_RAS_N
DDR_CAS_N
MEM_WR_N
MEM_BC1_N
MEM_BC0_N
DDR_DQS[1]
DDR_DQS[0]
MEM_AD[0]
MEM_AD[1]
MEM_AD[2]
MEM_AD[3]
MEM_AD[4]
MEM_AD[5]
MEM_AD[6]
MEM_AD[7]
MEM_AD[8]
MEM_AD[9]
MEM_AD[10]
MEM_AD[11]
MEM_AD[12]
MEM_AD[13]
MEM_AD[14]
MEM_AD[15]
MEM_CS0_N
MEM_RD_N
MEM_WR_N
MEM_WAIT_N
MEM_ADV_N
MEM_WP/
MEM_BUSY/
USIF1_SW
U403
FSA2259UMX
7
UART1_RX_IPC
2B0
6
GND
EUSY0186504
Only for training and service purposes