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3. With 128K bytes of display memory and A17 to A19 decoded internally to S1D13503;
MEMCS# = !REFRESH
Note: The MSBs of the address (A23:A20) need not be externally decoded if using SMEMW# and
SMEMR# as they will only assert on addresses < 1MB.
Additional Discrete Logic Description
1. As shown in Figure 1-1, the 74LS688 is configured as a memory decoder with valid addresses
between 0C0000h and 0DFFFFh. This provides the MEMCS16# signal allowing for 16-bit
memory cycles. As stated in the ISA specification, the MEMCS16# is a straight address decode
without qualification.
2. The 74LS09 is used simply to provide the Open-Collector outputs necessary for the IOCS16#
and MEMCS16# signals.
S1D13503 Default Setup
Configuration Options
The S1D13503 latches the state of the SRAM data bus during RESET to determine the power-on
configuration. The chip has internal pull-down resistors and therefore external pull-ups are only nec-
essary when requiring a '1' state, see below.
1. VD15–VD13 = 110
2. VD12–VD4 = 110001000
3. VD3 = 0
4. VD2 = 0
5. VD1 = 0
6. VD0 = 1
Where 1 = pull-up with a 10K resistor; 0 = no pull-up resistor
Register Setting
All register settings are completely programmable with the following exceptions;
- Memory Interface, AUX[1] bit 1 = 0 for 16-bit memory interface.
Note: This bit is forced = 0 when 16-bit CPU Interface is selected through VD0 on power-up.
- RAMS, AUX[1] bit 0, this bit is ignored in 16-bit memory configurations.
All other registers are dependent on display type, resolution, color and mode of operation, see
S1D13503 Hardware Functional Specification for details.
S18A-G-003-01
S1D13503 ISA Bus Interface Considerations
memory decoding for locations $C and $D segments
I/O decoding for locations 0310h and 0311h
(1100010000b–1100010001b)
No byte swap of high and low bytes
ISA Bus interface, i.e. non- MC68K interface
Indexed I/O
16-bit bus interface
5-3
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