Lvds Port (Cn6) - Asus AAEON GENE-SKU6 User Manual

16 GND
17 DP_AUX-
18 HPLG_DETECT
19 GND
20 +5V

2.7.4 LVDS Port (CN6)

*LVDS LCD_PWR can be set to +3.3V or +5V by JP4
Pin Pin Name
1 BKL_ENABLE
2 BKL_CONTROL
3 LCD_PWR
4 GND
5 LVDS_A_CLK-
6 LVDS_A_CLK+
7 LCD_PWR
8 GND
9 LVDS_DA0-
10 LVDS_DA0+
Chapter 2 – Hardware Information
GND
DIFF
IN
GND
I/O +5V
Signal Type Signal Level
OUT
OUT
PWR +3.3V/+5V
GND
DIFF
DIFF
PWR +3.3V/+5V
GND
DIFF
DIFF
24