LG 32LY560M Service Manual page 36

RESET
IC2101 3.3V_Proidiom
APX809-26SAG-7
021:O16
RESET VCC
2 3
FPGA_RESET
C2105
100
OPT 1
C2108
1uF R2105
1uF
GND
25V 25V
27MHz Clock
BMS-873R
X2100-*1
27MHz
+VCC TRI
4 1
3.3V_Proidiom OUTPUT GND
3 2
VCXO
X2100
27MHz
6 1
C2103 5 2
C2102
0.1uF
10uF
16V
6.3V 4 3
R2100 22
021:O16 DE_H_SYSCLK
Need to block pin no.2 & 5 of VCXO for stencil
+3.3V Pro:Idiom
+3.3V_Normal
3.3V_Proidiom
C2161
L2101 6.3V
OUT IN
GND
XMARK_1.8V
3.3V_Proidiom
IC2100
AZ1117BH-1.8TRE1
XMARK_1.8V
IN OUT
3 2
C2109
1
C2107
22uF
0.1uF
C2101 16V
C2100
16V
22uF 0.1uF ADJ/GND
16V 16V
GND
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
Copyright ⓒ 2014 LG Electronics. Inc. All right reserved.
Only for training and service purposes
Pro:Idiom
Only for LG1001
Parallel TP.
001:AJ25 TS_CLK
IO2_29/TP_SOP
001:AJ25 TS_VALID
IO2_21/TP_VALID
001:AJ25 TS_SYNC
IO2_17/TP_ERR
TS[0] IO2_41/TP_DATA[7]
001:AJ25 TS[0]
IO2_36/TP_DATA[6]
TS[1]
001:AJ25 TS[1]
TS[2]
IO2_31/TP_DATA[5]
001:AJ25 TS[2]
TS[3]
IO2_25/TP_DATA[4]
TS[3]
001:AJ25
TS[4]
IO2_23/TP_DATA[3]
001:AJ25 TS[4]
TS[5]
IO2_18/TP_DATA[2]
TS[5]
001:AJ25
TS[6]
IO2_14/TP_DATA[1]
001:AJ25 TS[6]
TS[7] IO2_8/TP_DATA[0]
TS[7]
001:AJ25
XMARK_1.8V
L2103
BLM18PG121SN1D
C2110
4.7uF
3.3V_Proidiom
PLL voltage R2118 10K
OPT
DE_H_SYSCLK
021:C20
IO2_48/RESET
021:B27 FPGA_RESET
R2125 22
IO3_37/I2C_SCK
R2126 0
3.3V_Proidiom FE_DEMOD_SCL IO3_34/I2C_SDA
FE_DEMOD_SDA R2127 0
CONF_DONE
IO1_22/ASDO
IO1_1/INIT_DONE
XMARK_1.8V
L2104
BLM18PG121SN1D
C2111
4.7uF
Full decap.: When use WATER MARK fuction
Half decap.: When do not use WATER MARK fuction
CLK1
H1
B8
B9
B10
C5
C6
C7
C8
C9
C10
C11
C12
IO1_29
M1
IO1_2
C3
IO1_3
C2
IO1_4
B1
IO1_5
G5
IO1_6
F4
IO1_7
D3
IO1_8
E4
IC1209
IO1_9
F5
IO1_10
E3
IO1_11
D2
IO1_12 LGDT1001
E2
CLK0
G1
B2
D14
E14
DCLK
K4
K13
NCONFIG
H3
NCE
J4
DATA0
H2
IO1_21SO
G4
K3
NCEO
H4
NSTATUS
J13
MSEL0
J3
MSEL1
J2
TCK
J14
TDO
H15
TMS
J15
TDI
H14
D4
IO1_13
D1
IO1_14
F3
IO1_15
G3
IO1_16
F2
IO1_17
E1
IO1_18
G2
IO1_19
F1
IO1_20
H5
IO1_23
J1
IO1_24
K2
IO1_25
L3
IO1_26
K1
IO1_27
L1
IO1_28
L2
IO1_30
N1
IO1_31
M2
IO1_32
N2
IO1_33
M3
IO1_34
L5
IO1_35
M4
Reduce decap.
16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V
IO4_34/CH_CLK
R11
IO4_20/CH_VALID
R8
IO4_26/CH_SOP
R9
IO4_30/CH_ERR
R10
IO4_8/CH_DATA[0]
P5
IO4_13/CH_DATA[1]
P6
IO4_18/CH_DATA[2]
P7
IO4_24/CH_DATA[3]
P8
IO4_28/CH-DATA[4]
P9
IO4_33/CH_DATA[5]
P10
IO4_35/CH_DATA[6]
P11
IO4_41/CH_DATA[7]
P12
IO2_34
E7
IO2_33
A6
IO2_32
B7
IO2_43
A4
IO2_30
D7
IO2_28
A8
IO2_27
E8
IO2_26
D8
IO2_44
B4
IO2_24
E10
IO2_45
C4
IO2_22
D9
IO2_20
A9
IO2_19
D10
IO2_16
A11
IO2_15
B11
IO2_46
B3
IO2_13
D11
IO2_12
D12
IO2_11
E9
IO2_10
E11
IO2_9
E12
IO2_47
A2
IO2_7
B12
IO2_6
A13
IO2_5
B13
IO2_4
C13
IO2_3
B14
IO2_2
A15
IO2_1
B15
IO3_43
D13
IO3_42
C14
IO3_41
C15
IO3_40
B16
IO3_39
G12
IO3_38
H13
IO3_36
E13
IO3_35
F12
IO3_33
D15
IO3_32
D16
IO3_31
E15
IO3_30
E16
R2141
IO3_29
F15
IO3_28
F13
IO3_27
F14
IO3_26
F16
IO3_25
G15
IO3_24
G13
IO3_23
G14
IO3_22
H12
CLK2
G16
CLK3
H16
3.3V_Proidiom
R2140 4.7K
DeCap close to IC
XXLY670H-UA
Pro:Idiom Block
3.3V_Proidiom
OPT
C2149
62pF
50V
001:AI27
R2135 100
PM_TS_CLK
R2136 100 001:AI27
PM_TS_VALID
R2137 100 001:AI27
PM_TS_SYNC
PM_TS[0]
PM_TS[1]
PM_TS[2]
PM_TS[3]
PM_TS[4]
PM_TS[5]
PM_TS[6]
PM_TS[7]
001:AI27
PM_TS[0-7]
INNER LAYER PATERN
XMARK_1.8V
L2113
BLM18PG121SN1D
0.1uF
C2148
DeCap close to IC
0.1uF
C2155
3.3V_Proidiom
4.7K
2013/08/17
21
LGE Internal Use Only