Sharp LC-32DH500 Service Manual page 34

LC-32DH500
2. Detailed ICs Information, DUNTKF261WE (Main Unit)
2.3. IC 1001 (MSD3303GX)
2.3.1. Key Features
• Master CPU with MMU.
• DRAM controller supporting up to two 16-bit DDR2 interface.
• Power control module with ultra low power MCU available in stand by mode.
• Parallel interface for external parallel NOR fl ash and NAND fl ash support.
• H.264 decoder. Support resolution up to HDTV ( 1080i, 720p) .
• MPEG-2 decoder.
• Video analog processor.
• NTSC/PAL/SECAM Video Decoder.
• Support Teletext mode.
• Two CVBS video outputs.
• Eight confi gurable CVBS, Y/C, S-video inputs.
• Multistandard sound Processor.
• AC3 decoder.
• I²S digital audio output.
• Six L/R audio line-inputs.
• SIF audio output.
• Stereo L/R output for main speaker.
• Two HDMI / HDCP compliant input port.
• CEC support.
• Fully programmable scaler and display processing.
• Support up to 10 bit LVDS full HDTV panel interface.
• Support USB 2.0
• Support Common Interface for conditional access.
2.3.2. Block Diagram
BS OUT x2
ANALOG
/YPBPR x3
FRONT-END
-VIDEO x8
TRANSPORT
IN (1P, 1S)
DEMUX
SIF
SIF IN x1 ADC
DEMOD
L/R x6 ADC
I2S INx1
PDIF IN x1
Processor *2
I2CS, JTAG I/F
NTSC/PAL/
H.264/
SECAM
RM
DECODER
MPEG2/
MPEG4
HW JPD
DDR2-16x2
DRAM I/F
DDR-2 DRAM
UART: x3
I2CM: x1
SPI: x1 (2 cs)
PWM: x4
PFLH: x1
DVB-CI: x1
(continued)
TV Encoder
INPUT
PROCESSING
VIDEO
PROCES
SING
GRAPHICS
ENGINE
AUDIO
DSP
AUDIO
DSP
USB 2.0 Power
HOST *2 Management
PHY I/F
IR, CEC, INT,
HSYNC, SARx4
34
DEINTERLACE
and SCALING
VIDEO
OUTPUT
CONTROLLER
VIDEO
PROCESSING
AUDIO
OUTPUT
CONTROLLER
10/100M
EMAC
MII or RMII
Dual LVDS
L/R OUT x3
S/PDIF OUT
I2S OUT