Philips 75PFL5704/F7 Service Manual page 61

Digital Main 2 Schematic Diagram [TYPE A]
1 NOTE:
The order of pins shown in this diagram is different from that of actual IC3001.
IC3001 is divided into eight and shown as IC3001 (1/8) ~ IC3001 (8/8) in this Digital Main Schematic Diagram Section.
DIGITAL MAIN CBA UNIT
4
C9006
1000P
JK9301
ANT-IN
C9001 C9002 C9018
L9007
470P 100P 100P
5.6nH
L9001 C9014 C9003 C9015
270nH VARISTOR 220P 2P
3
L9002
220nH
2
1
G
C9011 C9012
X9001
1000P 1000P
24MHz
1 4
2 3
18 17 16 15 14 13
L9003
270nH
19 RF-REF NU 12
C9022 C9021
C9004 L9004
1P 1P
220P 270nH
20 RF-IP 11
OUTPUT
I/F
C9017
1P
21 GND 10
C9005
220P
DSP
22 PGA ADC VCC 9
/FILTER
L9005 C9010 C9023
270nH 1000P 1P
23 GND GND 8
RF
L9006
AGC
270nH 24 NU VDDL 7
C9008 C9009
1000P 1
IC9001
SI2151 1 2 3 4 5 6
DIGITAL/ANALOG
TV TUNER
C9019 C9007
OPEN R9001 R9003 0.1
100 1K
R9002
C9020
100
OPEN
C3009 C3008
OPEN OPEN
H I
C9013 C9016 C9024 C9025
0.1 1 OPEN OPEN
R9005
100
R9004
100
C3014 C3013
33P 33P
C3006
OPEN
C3003 L3001
OPEN OPEN
C3005
OPEN
R3005
47
D3001 D3002 D3003
C3008A C3010 C3011
MM5Z5V6B MM5Z5V6B MM5Z5V6B
10 33P 33P
R3006
C3012 D3004 C3001
100
0.1 MM5Z5V6B 0.022
J
10-6
CN3002 (NO CONNECTION)
1 IF-AGC
2 SCL
3 SDA
4 GND
*1
IC3001(2/8)
MSD95UVGT4D-3-00FO
DIGITAL SIGNAL PROCESS
/MAIN MICRO CONTROLLER
C3004
R3001
0.1
OPEN
AC3
DEMODULATOR
/MPEG
C3002
R3003
0.1 DECODER
OPEN
AC2
TO DIGITAL TO DIGITAL
AD1 NU
MAIN 5 MAIN 5
IC3001(5/8) IC3001(5/8)
AD2 NU
R3004
47
AF4 NU
AG3 NU
R3007
2.7K
AG4 NU
AH2 NU
R3008
2.7K
AH3 NU
AG5 NU
AF5 NU
AF3 TU-SCL
AE4 TU-SDA
AC1 IF-AGC
R3002
L3003 10K
2.2uH
L3002
OPEN
C3007
0.1
CONTINUE
DIGITAL 8
P-ON+3.3V
K L
PL19.29ASCD2