HP 8340A Service Manual page 285

When the processor is ready for the next sweep,
HIGH. This causes LOW ENABLE RESET AMP 2 to go LOW. This forces
LRESET HIGH and LSPLD LOW,
At a bandcrossing,
which is coupled to HSP at U33C. This enables LOW ENABLE RESET
AMP 2, and LSPLD HIGH and LHLD LOW. This causes the ramp to
pause, but since LRSP is not pulled down by the processor,
Ramp does not reset. When the new information is written to the
Reset Register
the Reset Control Logic
the output o f U6
During the re-phase-lock routine,
LBX go HIGH. Then when it is ready for the next portion of the
sweep, it releases HSP. T his pulls LOW ENABLE RESET AMP 2 HIGH
which ultimately releases the output of U6. It also makes LHLD go
�IGH and LSPLD go LOW,
U33A and U33D are connected as an R/S flip-flop. As long as only
one of its inputs
. time, its outputs
TTL level. That is,
vice v�rsa. It would seem that U32D,
inverter, could be eliminated by connecting U33A pin 3 to U32D
pin 2. However,
LBX and HSP are HIGH while LRSP is LOW. This causes both outputs
of the flip-flop to be HIGH. Hence the need for U32D.
Current Shunt
When the voltage at the non-inverting input of U35B is a TTL
logic LOW, <1.4 volts,
This shunts the current coming through Q5,
Amplifier (Block
cannot discharge. When the input to U35B is a logic HIGH,
open collector output is pulled to +5 volts by RS. This reverse
biases CR3 so that no current is diverted away from C30.
Reset Amplifier
When the inverting input of U35A,
output of U35A is pulled to +20 volts by R36. This reverse biases
CRl allowing Q6 to turn on through R34. This closes the reset
loop shown in Figure
is connected to ground,
Ul4 to also be at ground. This ensures that Marker Ramp is at
zero volts at the
Model 8340A - service
and the sweep proceeds.
the A57 Marker/Bandcross board pulls down LBX,
(Block B), its strobe,
(Block
(Block L) to ground.
and the sweep continues.
(U33A pin 1,
(U33A pin 3,
if one is HIGH,
when the instrument is in the CW or MANAL mode,
Q
the output of U35B pulls to -10 volts.
J), through CR3 and back biases CR2 so that C30
1 R
80-19. Since the non-inverting input of Ul4
the loop forces the inverting input of
start of a sweep.
Scans by HB9HCA and HB9FSX
WRDAC, causes the output of
S) to go LOW which in turn forces
the instrument processor lets
U33D pin 12) is LOW at any given
U33D pin 11) will be the opposite
the other will be LOW,
which is used as an
in the virtual Ground
LRESET, is a TTL logic LOW,
it lets HSP go
Marker
and
its
the
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