Nokia RH-17 Series Troubleshooting - Bb page 7

RH-17
CCS Technical Documentation Troubleshooting — BB
3 By the RTC Alarm, when the RTC logic has been programmed to give an alarm
After receiving one of the above signals, the UEM counts a 20ms delay and then enters in
reset mode. The watchdog starts up, and if the battery voltage is greater than Vcoff+, a
200ms delay is started to allow references etc. to settle. After this delay elapses the
VFLASH1 regulator is enabled. Then, 500us later VR3, VANA, VIO and VCORE are enabled.
Finally the PURX (Power Up Reset) line is held low for 20 ms. This reset, PURX, is fed to
the baseband ASIC UPP, resets are generated for the MCU and the DSP. During this reset
phase, the UEM forces the VCTCXO regulator on — regardless of the status of the sleep
control input signal to the UEM. The FLSRSTx from the ASIC is used to reset the flash
during power-up and to put the flash in power-down during sleep.
All baseband regulators are switched on when the UEM powers on. The UEM internal
watchdogs are running during the UEM reset state, with the longest watchdog time
selected. If the watchdog expires, the UEM returns to power-off state. The UEM watch-
dogs are internally acknowledged at the rising edge of the PURX signal in order to always
give the same watchdog response time to the MCU.
The following timing diagram represents UEM start-up sequence from reset to power-on
mode.
Nokia Corporation
Issue 1 04/2003 Confidential Page 7