Sony KDL-26T3000 Service Manual page 36

P Q R S
FPGA WINGMAN
DGO8_AR
DRO9_AR
DRO8_AR
DEN_OUT_AR
DVS_OUT_AR
DHS_OUT_AR
DBO7_AR
DBO6_AR
JR5002
0
CHIP
JR5007
0
CHIP
5001
3.3V_MAIN
L5007
XX
DGO2
DRO3
DRO2
JL5002
DEN_OUT DEN_OUT
JL5003
DVS_OUT DVS_OUT
DHS_OUT JL5004
DBO9
DBO8
T U V W
0 . 1 0 . 1 0 . 1
C5026 C5027 C5030
PLACE AS CLOSE AS POSSIBLE
TO IC5002
Imax = 455mA
C5021
0 . 1
1000p
C5025
VCCA_PLL1
GND_1 GNDA_PLL1
10
C5018
GND
GNDA_PLL1
IO/LVDS77n/DEV_OE
IO/LVDS77p
OI/LVDS76p
IO/LVDS76n
IO/LVDS75p
IO/LVDS75n
1608
B
16V VCCIO4
0 . 1
C5022
IO/LVDS74p
X Y Z
GND_1
TP5028
TP5026 TP5029
TP5027
TP5025
TP5030
10k
R5015
JL5015JL5016
R5031
0
R5032
0
0
0
R5033
R5030
1608
B
16V
0 . 1
C5034
JL5023
0 . 1
C5031
0
R5059
XX
R5012
IO/LVDS16n
IO/LVDS16p
IO/LVDS17n/DEV CLRn
IO/LVDS17p
GND
IO/LVDS18p
VCCIO2
IO/LVDS18n
IO/LVDS19p
IO/LVDS19n
IO/LVDS23p
~ BC Board Schematic Diagram [ Tuner, Audio/Video Processor, HDMI & PC Input ] Page 6B/13 ~
- 35 -
AA BB CC DD
BC
6B/13
TP5031
R5016
10k
10k
R5017
FPGA_CONFIG
GND ASDI
VCC DCLK
DATA VCC
nCS VCC
IC5003
C5044
0 . 1
JR5001
0
JR5010
Imax = 2A 0
JL5024
L5010
XX
GND_1 JR5000
0
100
C5045
Imax = 2A
JR5011
0
JL5017
L5011
100
XX
C5046
GND_1
0 . 1 0 . 1 0 . 1
C5059 C5058 C5056
ADD CAPACITOR CLOSE VIAS PORT_A LINES (EMC)
R5022
100
TP5032 JL5020
TP5033 JL5021
R5023
100
R5019
100
XX
R5018
RB5016
0 . 1
10
C5039
EE FF
1
2
BC.SE1A
3
4
5
6
7
8
1.2V_MAIN
9
3.3V_MAIN
3.3V_MAIN
0 . 1
C5057
10
FPGA_CONF_DONE
SCL
SDA
11
FPGA_RESETQ
PORT_A_A29_R9
PORT_A_A28_R8
PORT_A_A27_R7
PORT_A_A26_R6
12
PORT_A_A25_R5
PORT_A_A24_R4
PORT A A23 R3