Electrical Troubleshooting Guide & Waveforms; System Clock X501 (27Mhz); Initializing Between Mpeg And Sdram - Zenith DVB318 Service Manual

ELECTRICAL TROUBLESHOOTING GUIDE & WAVEFORMS

1. System Clock X501 (27Mhz)

NORMAL
1) MPEG IC start oscilating
after being installed VCC
6.5 Vp-p
X501 : 27 Mhz

2. Initializing between MPEG and SDRAM

1) MPEG IC start oscilating(27Mhz)after being
installed VCC
2) MPEG IC and DSP IC get the /M - RESET sig-
nal from front µ-com and they are initialized.
3) And then, MPEG IC generate SMI_CLK and
send to SDRAM
Front
µ-com
/M-RESET
IC501
L507
MPEG
(STI5589)
SMI_CLK
X501
IC501
MPEG
(STI5589)
X501
/M-RESET
(27 Mhz)
IC502
SDRAM
SMI_CLK
(133 Mhz)
ABNORMAL
1) Logo Picture doesn't appear
2) Initial step fail
* Initial step : power cord in -> green LED ->
OFF -> power key input -> Logo picture
X501 : there is distortion
4) MPEG IC and SDRAM are synchronized by
SMI_CLK, they communicate between.
If oscilation(27Mhz) don't appear, check
The X-TAL and VCC and replace MPEG IC.
If SMI_CLK don't appear, first cut the SMI_CLK
line (remove L507) and recheck.
Don't appear -> check MPEG IC or replace
Appear -> check the SDRAM or replace
Power
Cord in
X501
3-2
Reset Time