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• Refer to page 4-3 (English), 4-4 (Japanese) for mark 0.
1
2
3
4
MD-134 BOARD (3/8)
A
RF PROCESS
XX MARK:NO MOUNT
R4145
NO MARK:REC/PB MODE
XX
R:REC MODE
Q4101
P:PB MODE
MCH3309-TL-E
4.1
B+ SWITCH
R:4.1/P:0
R4142
R:0/P:4.1
10k
B
R:2.8/P:0
FB4107
Q4102
UNR32A300LS0
REG_GND
A_2.5V
C
D_2.5V
(7/8)
DRV_A_4.1V
D_2.8V
CN4101
51P
VC
1
VC
2
D
NC
3
NC
4
VCC
5
VCC
6
C4101
NC
7
1u
NC
8
GND
9
GND
10
E
NC
11
NC
12
PDB
13
FVREF
PDB
14
GSW
15
R4128 0
e
16
R4126 0
d
17
R4125 0
c
18
F
R4130 0
j
19
R4129 0
i
20
R4131 0
h
21
CL4120
FMON
22
R4124 0
a
23
R4127 0
b
24
DVD
RF+
25
MECHANISM
RF-
26
DECK
G
(DDX-U1000)
GND3
27
(1/2)
GND3
28
GND3
29
GND3
30
FL4111
NC
31
1
2
NC
32
4
3
VCC_LD
33
C4104
VCC_LD
34
10u
H
C4143
VCC_LD
35
XX
FL4112
NC
36
2
1
NC
37
3
4
R4134
VCC1
38
XOUTEN3
39
C4137
R4133
VCC1
40
XX
XOUTEN2
41
VCC1
42
R4132
I
XOUTEN1
43
C4103
VCC1
44
XX
TEMP
45
CL4123
OSCEN
46
R4101
XX
XPS
47
IINR
48
VWDC1
IIN1
49
VWDC2
IIN2
50
J
VWDC3
IIN3
51
DVD MECHANISM DECK is replaced
as block,so that there PRINTED
WIRING BOARD and SCHEMATIC
DIAGRAM are omitted.
@113
(5/8)
BATT_IN
(7/8)
D4101
XX
K
WP3_OP
WP3_OP
WP2_OP
WP2_OP
WP1_OP
@109
WP1_OP
TEMP
TEMP
(1/8)
OSCEN
OSCEN
LD_EN
LD_EN
L
05
HDR-UX3E/UX5/UX5E/UX7/UX7E_L3
5
6
7
:Voltage measurement of the CSP ICs
and the Transistors with mark,are
not possible.
Q4102,Q4103
SLEEP SWITCH
Q4103
UNR32A300LS0
R4143
10k
R4144
10k
R:0/P:2.8
L4103
4.7uH
A_2.5V
C4113
C4114
10u
10u
C4112
10u
L4102
4.7uH
B2
A2
DRV_A_4.1V
HAVCC
C4109
C4115
0.1u
DRFP
0.1u
DRFP
DRFN
DRFN
C4110
GSW
0.1u
GSW
GSW
CL4119
VCC
E
C4119
0.1u
C
A
A
B
B
B
G
F
C
C
H
D
D
FPDO
A
E
E
D
F
F
DRFP
DRFN
G
G
H
H
APCLOAD
APCLOAD
C4116
10u
HAVC
TESTOUTN
C4140
0.1u
GND
C4141
0.1u
TESTOUTP
C4117
10u
ADVC
VC
VC
0
WP3_OP
C4118
10u
0
WP2_OP
0
WP1_OP
L2
M2
TEMP
FB4103
OSCEN
C4111
D_2.5V
LD_EN
10u
VRDC
8
9
10
11
C4120
C4121
C4122
C4123
C4124
0.1u
0.01u
0.1u
0.01u
0.1u
CL4103
C4127
C4128
0.1u
100p
B3
A3
B4
A4
B5
A5
B6
A6
B7
A7
B8
A8
B9
A9
B10
A10
A11
A12
PH1
BH1
PI
FE
TE
VCC
CE
BGIREF
VTIREF
IC4101
AUX1
RF PROCESS
IC4101
GND
CXA2725GA-T4
MPXOUT1
MPXOUT2
SWRF
AWBL
LPPC
AGC3C
AGC2C
AGC1C
VDD
L3
M3
L4
M4
L5
M5
L6
M6
L7
M7
M8
L8
M9
L9
M10
L10
M11
L11
CL4114
CL4110
CL4111
CL4112
R4138
0
4-30
12
13
14
15
TXD
RXD
JNTRST_J
@111
JTDI_J
JTMS_J
(1/8)
JTCK_J
JRTCK_J
JTDO_J
MNT4
MNT5
MNT6
@106
MNT7
MNT1
(1/8)
MNT2
SV_NOISE
SLEEP_SW_OP
EQRF_S
BH2
C4138
39p
PH2
PH1
BH1
PI
R4139
0
FE
TE
R4140
0
CE
R4122
22k
C4134
0.1u
R4123
22k
MPXOUT1
@112
MPXOUT2
CL4128
(1/8)
SWRF
AWBL
WLDON
WLDON
C4129
0.001u
LPP2
LPP2
C4130
LPP
LPP
0.1u
DWBL
DWBL
C4131
0.1u
RECD1
RECD1
C4132
XRST_IC_4101
XRST_IC_4101
0.1u
SCS
SCS
C4133
0.1u
SCLK
SCLK
C4135
SDAT
SDAT
10u
APCLOAD
APCLOAD
VC
VC
ATTPLS
R4137
ATTPLS
10k
ROPCSH
ROPCSH
D_2.8V
MSPDSH
MSPDSH
RFPDSH
RFPDSH
FB4104
WFPDSH
WFPDSH
RFMCLK
RFMCLK
@114
XDR_RESET
(5/8)
@101
BOOTSEL
DEW_AD
(1/8)
(5/8)
@115
VTR_UNREG
(6/8)
(7/8)
16
17
18
CN4014
14P
1
TRST_J
2
JTDI_J
3
JTMS_J
4
JTCK_J
5
JRTCK_J
6
JTDO_J
7
MNT4
CPC
(For Check)
8
MNT5
9
MNT6
10
MNT7
11
PI
12
FE
13
TE
14
CE
CN4017
XX
6
DEW_AD
5
DEW_AD
4
N.C
3
REG_GND
2
REG_GND
N.C
1
CN4013
14P
1
MPXOUT1
2
MPXOUT2
3
XDR_RESET
4
BOOTSEL
5
MNT1
6
MNT2
7
TXD
CPC
8
RXD
(For Check)
9
SV_NOISE
10
REG_GND
11
TESTOUTN
12
D_2.8V
TESTOUTP
13
14
VTR_UNREG
MD-134 (3/8)
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