Sony MEX-GS610BE Service Manual page 45

Pin No. Pin Name
62 DVSS5
63 VDD1-3
64 VSS-2
65 XVSS3
66 XI
67 XO
68 XVDD3
69 ADVDD3
70 ADIN1 (IN_L-CH)
71 ADVREFL
72 ADVCM
73 ADVREFH
74 ADIN2 (IN_R-CH)
75 ADVSS3
76 MS
77, 78 CD_BUS0, CD_BUS1
79 CD_BUS2
80 CD_BUS3
81 CD_BUCK
82 CD_XCCE
83 VDD3-2
84 VSS-3
85 /RST
86 VDD1-4
87 DEC_INT
88 BSIF_INT
89 BSIF_GATE
90 BSIF_DATA
91 BCK_IN_F
92 LRCK_IN_F
93 DEC_XMUTE
94 ZDET
95 SP_DATA
96 SP_CLK
97 TEST
98 PDO
99 TMAX
100 LPFN
I/O
- Ground terminal
- Power supply terminal (+1.5V)
- Ground terminal
- Ground terminal
I System clock input terminal (16.9344 MHz)
O System clock output terminal (16.9344 MHz)
- Power supply terminal (+3.3V)
- Power supply terminal (+3.3V)
I Audio signal (L-ch) input from the electrical volume
O Reference voltage output terminal
O Reference voltage output terminal
O Reference voltage output terminal
I Audio signal (R-ch) input from the electrical volume
- Ground terminal
Microprocessor interface mode selection signal input terminal
I
"L": serial interface, "H": parallel interface
I/O Serial data input/output terminal
O Serial data output to the system controller
I Serial data input from the system controller
I Serial data transfer clock signal input from the system controller
I Chip enable signal input from the system controller
- Power supply terminal (+3.3V)
- Ground terminal
I Reset signal input from the system controller
- Power supply terminal (+1.5V)
O Interrupt signal output to the system controller
O Request signal output to the system controller
I Gate signal input from the system controller
I Audio data input from the system controller
I Bit clock signal input from the system controller
I L/R sampling clock signal input from the system controller
I Muting on/off control signal input from the system controller
O Zero data detection signal output to the system controller
O Serial data output to the system controller
I Serial data transfer clock signal input from the system controller
I Test mode setting terminal
O EFM and PLCK phase difference signal output terminal
O TMAX detection result output terminal
I PLL circuit low-pass fi lter amplifi er inversion input terminal
MEX-GS610BE/GS610BT/N6050BT
Description
Fixed at "L" in this unit
Not used
"L": reset
Normally fi xed at "L"
"L": muting on
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