JVC GZ-MC200US Schematic Diagrams page 18

ANALOG(SUB CPU) SCHEMATIC DIAGRAM
TO REG
TO CN208
REG_3.1V
5
TO CN203, 208
SJIG_RST
4
TO AUDIO
VOIC_LED
TO CN209
CHRG_LED
TO CN207
ACES_LED
TO ANA IF
TALY_LED
TO CN203
3
REG_DATA
TO CN208
TO CN209
TO TL202
LCD_OPEN
2
TO CN203
SCPU_SCK
TO CN208
FLSH_RST
TO CN203
1
NOTES: 1. For the destination of each signal and further line connections that are cut off from this diagram, refer to "BOARD INTERCONNECTIONS".
2. The parts with marked ( ) is not used.
A
2-17
LIT_3V
BATT_L
ADP_L
L1001
10µ
AL_3.3V
L1002
0.1
GND
C1037 C1001 C1002
10/ 6.3V 10/ 6.3V
R1002
Q1001
2SC4617/QR/-X
UN9212J-X
R1005 10K DTC124EE-X
PDTC124EE-X
R1006
4.7K
BUZZER Q1002
STIL_LED
VIDE_LED
VPP
REG_CLK
SN74LV86ADGV-X
R1054
POFF_SW
R1052 1K 100K
R1053 1K 100K
R1055
SCPU_SI
SCPU_SO
REG_CS
DSP_RST
B
10µ
0.1
100K
C1003
R1001
IC1002
S-80823CNNB-G-W
R1003
150K 2.7K
18K
R1004
D1001
DA221-X
C1006
1
R1039 470
R1025 470
R1015 470
R1008 2.2K
R1049 470
IC1006
R1011
C1011
100K 0.01
C1012
0.01
C1013
0.01
C1014
0.01
C1020 C1015
0.01 0.01
C1016
0.01
C1017
0.01
IC1003
RS5C314-X
CS VDD X1002
NAX0491-001X
CLK Xin
SIO Xout
VSS INTR
C1005
8p
C1007
C1010
R1048
2.2K
NAX0647-001X
X1001
C
IC1004
SN74LV32ADGV-X
0.01
C1008
V_BATT
T_BATT
I_MTR
KEY_C
VPP
AVDD
VDD
OSC2
OSC1
VSS
XI
XO
MMOD
RESET
REG_DA
RTC_DA
D