Denon AVR-E200 Service Manual page 74

CS497024CVZ Block diagram
M12L16161A5TG (DIGITAL : IC83)
M12L16161A5TG Terminal Functions
Pin
CLK System Clock
CS Chip Select
CKE Clock Enable
A0 ~ A10/AP Address
BA Bank Select Address
RAS Row Address Strobe
CAS Column Address Strobe
WE Write Enable
L(U)DQM Data Input / Output Mask
DQ0~15 Data Input / Output
VDD/VSS Power Supply/Ground
VDDQ/VSSQ Data Output Power/Ground
N.C/RFU No Connection/ Reserved for Future Use This pin is recommended to be left No Connection on the device.
Name
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except CLK, CKE
and L(U)DQM.
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
Row / column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA10, column address : CA0 ~ CA7
Selects bank to be activated during row address latch time. Selects bank for read/write
during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and row precharge. Latches data in starting from CAS , WE active.
Makes data output Hi-Z, t
Blocks data input when L(U)DQM active.
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide improved noise immunity.
Input Function
after the clock and masks the output.
SHZ
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