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Clock Fail
Check the 16.8MHz reference clock by measuring the signal via C1994 (Nominal 1.0 Vp-p sine-
wave)
If 16.8MHz clock is not probed, check the reference oscillator part of RF side.
Depress PWR button, then Check the clock from the CIA as below
CLK0 : 5.6Mhz CRIB input clock
CLK1: 32.749khz RF dither circuit clock (measured via R332)
CLK2: 32.749khz MCU input clock
CLK3: 1.12Mhz DSP input clock
CHIPx8: 9.8304Mhz Chipx8 clock (measured via TP1911)
Check the 32.768khz crystal clock (measured via R1142)
32khz_Buff_out: 32.768khz sleep mode clock out (measured via TP1130)
Casper 68338 PLL locking
Verify the 68338 CPU PLL locking by measuring the XFC signal through C1154
After Logic 2.75V &1.8V supplied to Casper U1100, XFC level shall be 650-700mV
After RESETB signal released, XFC level shall be 850-900mV within 10ms of CPU start.
If PLL locking is failed, Replace the U1100 Casper or Check the PLL circuit (C1152, C1153, C1154,
R1151)
Phone is not powered on (3)
Check Watchdog
Check watchdog level from CASPER to CCAP lite by measuring the WDI level via R1181.
Depress PWR button, then the WDI signal maintain 'Low' for approximately 270~280 msec after
power on and goes to 'High'
Take off the R1181 0Ohm resister and put the 1kOhm resister to the R1180 DNP
Check if the phone operate normally.
If the phone is not powered on and logic_2.75 doesn't go down, it show the program does not
perform normally (Casper, Memory, CIA etc.or Software failure)
Check the phone mode
Check the manual test line via R1178
If the manual test line is 'Low', the phone will go to flash mode and if 'High', the phone will go
to the normal turn on sequence.
In flash mode, if the flash programmer recognize the phone UART, the possible defect is on the
65
(measured via TP1915)
(measured via TP1913)
(measured via TP1912)
Troubleshooting
4/3/01
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