Panasonic DLP PT-D5500U Service Manual page 55

14.3. Signal Processing (2/2)
Signal Processing (2/2)
4
1
IC3042
(FPGA)
VIDEO SIGNAL PROCESSOR,
2
SYNC SIGNAL PROCESSOR,
TEST PATTEN GENERATOR
4
3
4
3
5
LAMPLITZ
CPUIICSEL1
IIC
CPUIICSEL2
SELECTORS
CPUIICSEL3
256K
IC2502,
EEPROM
IC2503
IC2508
6
IC2522
EXT.
I/O
RESET_SH2
SDA SCL
2
7
A-P.C.Board FM-Module
IC3044
A41 FM1
LVDS
OUTPUT
A40 FM3
CWINDEX
IC2507
3
ASI
2
MAIN CPU
4
2
3
8M 256K EXT.
RESET
FLASH SRAM OUTPORT
IC2506 IC2509 IC2511, IC2516,
IC2512 IC2517
IC4004 IC4006
FLASH
RDRAM
MEMORY
IC4001 IC4002
LVDS DMD FORMATTER
RECEIVER CONTROL
IC4010 IC4003
POWERGOOD2
DMD MIRROR
FMRST DRIVE
BUFFERS
LAMPLITZ
A2
A1
A3
IC2505
REMOTE_IN
CPUASO
ASO
BUFFERS
ASCLK
CPUASCLK
REMOTE_RE2
CPU232C_IN_TXD
CPU232C_OUT_TXD
CPU232C_IN_RXD
CPU232C_OUT_RXD
IIC SDA
IIC SCL
2
55
PT-D5500U / PT-D5500E / PT-D5500UL / PT-D5500EL
R-P.C.Board
IC4008
R1
DMD
0.7 inch
XGA DDR
S-P.C.Board
SWITCHES
S1
IC9803
IIC SDA
8
EXT.
I/O
IIC SCL
IC9804
5V
Q9803
AMP
IC9805 IC9806
IC9802
J1
AMP
Q9801,
IC9801
Q9802
RIN1
DIN1
DOUT1
DIN2
ROUT1
ROUT2
DOUT2
RIN2
J-P.C.Board
REMOTE 2
IN
IN
REMOTE 1
OUT
3
IN
2
SERIAL
3
OUT
2