Schematic Diagram; Cd Servo Circuit - Panasonic SA-AK200 Schematic Diagram

SCHEMATIC DIAGRAM - 2

CD SERVO CIRCUIT

C723
10V220
C724
0.1
<3.2V>((0V))
<1.5V>((0V))
<1.5V>((0V))
X701 R714
RSXZ16M9M01T
0 <0V>((0V))
<0V>((0V))
C722 C721
10P 10P
<0V>((0V))
<0V>((0V))
<0V>((0V))
<0V>((0V))
<0V>((0V))
<3.2V>((0V))
C718 R712
C717
C744
0.22 220 <0V>((0V))
0.1
5600P
<0.5V>((0V))
<1.6V>((0V))
R741
R711
R709
82K
47K <1.6V>((0V))
47K
<1V>((0V))
<1.6V>((0V))
C716
<0V>((0V))
820P
<1.5V>((0V))
R742
220K <0V>((0V))
: +B SIGNAL LINE
: CD-DA SIGNAL LINE
R721
100
C731
6.3V220
C730
0.1
C754
470P
61 62 63 64 65 66 67 68 69 70 71
60 VDD
59 X2 OUT
58 X1 IN
57 VSS
56 SBCK
55 SUBC
54 VCOF2
PCK IC702
53
EFM
52 MN662790RSC
SERVO PROCESSOR
51 AVSS2
DIGITAL SIGNAL PROCESSOR/
50 AVDD2
DIGITAL FILTER/
D/A CONVERTER
VCOF
49
48 PLLF
DSLF
47
DRF
46
45 IREF
ARF
44
43 WVEL
42 DSLF2
41 PLLF2
40 39 38 36 34 33 32 31
37 35
TJ702
: CD SIGNAL LINE
R717
1K C725
1000P
C726
1000P
R718
1K
C732 C733
6.3V220
72 73 74 75 76 77 78 79 80
BCLK
1
<0V>((0V))
LRCK 2
<0V>((0V))
SRDATA 3
<0V>((0V))
DVDD1 4
<3.2V>((0V))
DVSS1
5
<0V>((0V))
6
TX
<1.6V>((0V))
MCLK 7
<3.2V>((0V))
MDATA
8
<0.5V>((0V))
MLD 9
<3.2V>((0V))
SENSE 10
<0V>((0V))
/FLOCK
11
<0V>((0V))
/TLOCK 12
<0V>((0V))
BLKCK 13
<0V>((0V))
SQCK 14
<0V>((0.2V))
SUBQ
15
<3.2V>((3.1V))
DMUTE 16
<0V>((0V))
STAT 17
<0V>((3.1V))
/RST 18
<3.1V>((0V))
19
SMCK
<0V>((0V))
CSEL 20
<0V>((0V))
30 29 28 27 26 25 24 23 22 21
19
23
C727
50V1
22
21
C728
50V1
0.1
17
C753
470P
C743
0.1
8
7 6
4
R753
11
100
10
9
C745
1000P
S701
RESET SW
16
20
18
19
LCH OUT
18
A.GND
17
RCH OUT
16
+3.3V
15
D.GND
14
LD SW
13
TX
12
TO
+7.5V
MAIN
11
P.GND
CIRCUIT
10
(CN310) ON
MCLK
SCHEMATIC
9
MDATA
DIAGRAM-5
8
MLD
7
SPEED
6
BLKCK
5
SQCK
4
SUBQ
3
STAT
2
/RST
1
RESET
SW
CN702
3
1
15