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A
<27>
PCIE_PRX_DTX_N2
<27>
PCIE_PRX_DTX_P2
WLAN
C170
<27>
PCIE_PTX_C_DRX_N2
C171
<27>
PCIE_PTX_C_DRX_P2
<25>
PCIE_PRX_DTX_N3
<25>
PCIE_PRX_DTX_P3
1
PCIE LAN
C169
<25>
PCIE_PTX_C_DRX_N3
C174
<25>
PCIE_PTX_C_DRX_P3
+3VS
R121
2
1
10K_0402_5%
MINI1_CLKREQ#
2
1
R123
10K_0402_5%
PCH_GPIO20
+VCCSUS3_3
2
1
PCH_GPIO73
R124
10K_0402_5%
R126
2
@
1
10K_0402_5%
LAN_CLKREQ#
R127
2
1
10K_0402_5%
PCH_GPIO26
2
1
R128
10K_0402_5%
PCH_GPIO44
R129
2
1
10K_0402_5%
PCH_GPIO45
2
1
PCH_GPIO46
R130
10K_0402_5%
2
1
R142
10K_0402_5%
PCH_GPIO56
2
No use PU 10K +3VALW
<27>
CLK_PCIE_MINI1#
<27>
CLK_PCIE_MINI1
WLAN
<27>
MINI1_CLKREQ#
No use PU 10K +3VS
No use PU 10K +3VS
<25>
CLK_PCIE_LAN#
PCIE LAN
<25>
CLK_PCIE_LAN
No use PU 10K +3VALW
<25>
LAN_CLKREQ#
No use PU 10K +3VALW
No use PU 10K +3VALW
3
No use PU 10K +3VALW
No use PU 10K +3VALW
4
A
B
U16B
BG34
PERN1
BJ34
PERP1
AV32
PETN1
AU32
PETP1
PCIE_PRX_DTX_N2
BE34
PERN2
PCIE_PRX_DTX_P2
BF34
PERP2
1
2
0.1U_0402_16V7K
PCIE_PTX_DRX_N2
BB32
PETN2
1
2
PCIE_PTX_DRX_P2
AY32
0.1U_0402_16V7K
PETP2
PCIE_PRX_DTX_N3
BG36
PERN3
PCIE_PRX_DTX_P3
BJ36
PERP3
1
2
0.1U_0402_16V7K
PCIE_PTX_DRX_N3
AV34
PETN3
1
2
PCIE_PTX_DRX_P3
AU34
0.1U_0402_16V7K
PETP3
BF36
PERN4
BE36
PERP4
AY34
PETN4
BB34
PETP4
BG37
PERN5
BH37
PERP5
AY36
PETN5
BB36
PETP5
BJ38
PERN6
BG38
PERP6
AU36
PETN6
AV36
HM70 not support
PETP6
PCIE port 5-8
BG40
PERN7
BJ40
PERP7
AY40
PETN7
BB40
PETP7
BE38
PERN8
BC38
PERP8
AW 38
PETN8
AY38
PETP8
Y40
CLKOUT_PCIE0N
Y39
CLKOUT_PCIE0P
J2
PCH_GPIO73
PCIECLKRQ0# / GPIO73
AB49
CLKOUT_PCIE1N
AB47
CLKOUT_PCIE1P
M1
MINI1_CLKREQ#
PCIECLKRQ1# / GPIO18
AA48
CLKOUT_PCIE2N
AA47
CLKOUT_PCIE2P
PCH_GPIO20
V10
PCIECLKRQ2# / GPIO20
Y37
CLKOUT_PCIE3N
Y36
CLKOUT_PCIE3P
LAN_CLKREQ#
A8
PCIECLKRQ3# / GPIO25
Y43
CLKOUT_PCIE4N
Y45
CLKOUT_PCIE4P
PCH_GPIO26
L12
PCIECLKRQ4# / GPIO26
V45
CLKOUT_PCIE5N
V46
CLKOUT_PCIE5P
L14
PCH_GPIO44
PCIECLKRQ5# / GPIO44
AB42
CLKOUT_PEG_B_N
AB40
CLKOUT_PEG_B_P
E6
PCH_GPIO56
PEG_B_CLKRQ# / GPIO56
V40
CLKOUT_PCIE6N
V42
CLKOUT_PCIE6P
PCH_GPIO45
T13
PCIECLKRQ6# / GPIO45
V38
CLKOUT_PCIE7N
V37
CLKOUT_PCIE7P
PCH_GPIO46
K12
PCIECLKRQ7# / GPIO46
AK14
CLKOUT_BCLK0_N / CLKOUT_PCIE8N
AK13
CLKOUT_BCLK0_P / CLKOUT_PCIE8P
COUGARPOINT_FCBGA989
HM77@
B
C
E12
SMB_ALERT#
SMBALERT# / GPIO11
SMB_ALERT#
H14
PCH_SMBCLK
SMBCLK
PCH_SMBCLK
C9
PCH_SMBDATA
SMBDATA
PCH_SMBDATA
A12
RST_GATE
RST_GATE
SML0ALERT# / GPIO60
C8
S3 reduse
SML0CLK
G12
SML0DATA
C13
PCH_GPIO74
S3 reduse
SML1ALERT# / PCHHOT# / GPIO74
E14
PCH_SML1CLK
SML1CLK / GPIO58
M16
PCH_SML1DATA
SML1DATA / GPIO75
M7
CL_CLK1
T11
CL_DATA1
P10
CL_RST1#
M10
PCH_GPIO47
PEG_A_CLKRQ# / GPIO47
AB37
CLKOUT_PEG_A_N
AB38
CLKOUT_PEG_A_P
AV22
CLK_CPU_DMI#
CLKOUT_DMI_N
CLK_CPU_DMI#
AU22
CLK_CPU_DMI
CLKOUT_DMI_P
CLK_CPU_DMI
AM12
CLK_CPU_DPLL#
CLKOUT_DP_N / CLKOUT_BCLK1_N
CLK_CPU_DPLL#
AM13
CLK_CPU_DPLL
CLKOUT_DP_P / CLKOUT_BCLK1_P
CLK_CPU_DPLL
BF18
1
CLK_BUF_CPU_DMI#
R131
CLKIN_DMI_N
BE18
CLK_BUF_CPU_DMI
R132
1
CLKIN_DMI_P
BJ30
1
CLKIN_GND1#
R133
CLKIN_DMI2_N
BG30
1
CLKIN_GND1
R134
CLKIN_DMI2_P
G24
CLK_BUF_DREF_96M#
1
R135
CLKIN_DOT_96N
E24
1
CLK_BUF_DREF_96M
R136
CLKIN_DOT_96P
AK7
CLK_BUF_PCIE_SATA#
R137
1
CLKIN_SATA_N / CKSSCD_N
AK5
CLK_BUF_PCIE_SATA
1
R138
CLKIN_SATA_P / CKSSCD_P
K45
CLK_BUF_ICH_14M
R139
1
REFCLK14IN
H45
CLK_PCI_LPBACK
CLKIN_PCILOOPBACK
V47
XTAL25_IN
XTAL25_IN
V49
XTAL25_OUT
XTAL25_OUT
W=12mil S=15mil
90.9_0402_1%
Y47
XCLK_RCOMP
1
XCLK_RCOMP
K43
CLK_FLEX0
@
CLKOUTFLEX0 / GPIO64
T12
PAD
F47
CLK_FLEX1
@
PAD
CLKOUTFLEX1 / GPIO65
T13
H47
CLK_FLEX2
@
PAD
CLKOUTFLEX2 / GPIO66
T14
K49
CLK_FLEX3
@
T33
PAD
CLKOUTFLEX3 / GPIO67
Compal Secret Data
Compal Secret Data
Compal Secret Data
Security Classification
Security Classification
Security Classification
2011/11/22
2011/11/22
2011/11/22
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
D
No use PU 10K +3VALW
SMB_ALERT#
<29>
PCH_SMBCLK
DDR,WLAN,SMBUS
<27>
PU 2.2K +3VALW
PCH_SMBDATA
<27>
RST_GATE
PCH_GPIO74
<6>
PCH_SML1CLK
No use PU 10K +3VALW
PCH_SML1DATA
PCH_GPIO47
No use PU 10K +3VALW
EC-PCH SMBUS
PU 2.2K +3VALW
PCH_SMBDATA
6
Q5A
DMN66D0LDW-7_SOT363-6
PCH_SMBCLK
DMN66D0LDW-7_SOT363-6
No use PU 10K +3VALW
PCH_SML1DATA
6
<5>
Q6A
<5>
DMN66D0LDW-7_SOT363-6
<5>
120MHz for eDP.
PCH_SML1CLK
<5>
2
10K_0402_5%
DMN66D0LDW-7_SOT363-6
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
Pull down 10K ohm
for using internal Clock
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
CLK_PCI_LPBACK
2
1
1
2
R140
@
C175
@
22P_0402_50V8J
33_0402_5%
Reserve for EMI please close to PCH
+1.05VS_VTT
R141
2
XTAL25_IN
XTAL25_OUT
R144
25MHZ_10PF_7V25000014
3
1
C176
12P_0402_50V8J
2
2012/11/22
2012/11/22
2012/11/22
Title
Title
Title
Deciphered Date
Deciphered Date
Deciphered Date
Size
Size
Size
Document Number
Document Number
Document Number
Custom
Custom
Custom
Date:
Date:
Date:
D
E
+VCCSUS3_3
R113
1
2
10K_0402_5%
R114
1
2
2.2K_0402_5%
1
2
R115
2.2K_0402_5%
R116
1
2
1K_0402_5%
1
2
R117
10K_0402_5%
R118
1
2
2.2K_0402_5%
1
R119
1
2
2.2K_0402_5%
1
2
R120
10K_0402_5%
+3VS
For DDR , TP
R122
4.7K_0402_5%
1
2
+3VS
1
D_CK_SDATA
D_CK_SDATA
<11,12,30>
R125
4.7K_0402_5%
1
2
+3VS
3
4
D_CK_SCLK
D_CK_SCLK
<11,12,30>
Q5B
+3VS
Pull up at EC side.
2
1
EC_SMB_DA2
EC_SMB_DA2
<29>
3
4
EC_SMB_CK2
EC_SMB_CK2
<29>
Q6B
<17>
3
1
2
1M_0402_5%
1
3
1
GND
GND
1
4
2
Y2
C177
12P_0402_50V8J
2
4
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
PCH (2/9) PCIE, SMBUS, CLK
PCH (2/9) PCIE, SMBUS, CLK
PCH (2/9) PCIE, SMBUS, CLK
Rev
Rev
Rev
Q1VZC M/B LA-8941P Schematic
Q1VZC M/B LA-8941P Schematic
Q1VZC M/B LA-8941P Schematic
1.0
1.0
1.0
Friday, April 20, 2012
Friday, April 20, 2012
Friday, April 20, 2012
Sheet
Sheet
Sheet
14
14
14
of
of
of
45
45
45
E
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