Texas Instruments TPS7A8300EVM-209 User Manual
Texas Instruments TPS7A8300EVM-209 User Manual

Texas Instruments TPS7A8300EVM-209 User Manual

Evaluation module

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This user's guide describes the operational use of the TPS7A8300EVM-209 Evaluation Module (EVM) as
a reference design for engineering demonstration and evaluation of the TPS7A8300, low dropout linear
regulator (LDO). Included in this user's guide are setup instructions, a schematic diagram, layout, thermal
guidelines, and bill of materials (BOM).
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Thermal Resistance, θ
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Table 2. TPS7A8300EVM-209 BOM
SLVU919 - June 2013
Submit Documentation Feedback
TPS7A8300EVM-209 Evaluation Module
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, and Maximum Power Dissipation
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Copyright © 2013, Texas Instruments Incorporated
Contents
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List of Figures
List of Tables
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TPS7A8300EVM-209 Evaluation Module
User's Guide
SLVU919 - June 2013
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Summary of Contents for Texas Instruments TPS7A8300EVM-209

  • Page 1: Table Of Contents

    SLVU919 – June 2013 TPS7A8300EVM-209 Evaluation Module This user’s guide describes the operational use of the TPS7A8300EVM-209 Evaluation Module (EVM) as a reference design for engineering demonstration and evaluation of the TPS7A8300, low dropout linear regulator (LDO). Included in this user’s guide are setup instructions, a schematic diagram, layout, thermal guidelines, and bill of materials (BOM).
  • Page 2: Introduction

    Introduction The Texas Instruments TPS7A8300EVM-209 EVM helps design engineers to evaluate the operation and performance of the TPS7A8300 family of linear regulators for possible use in their own circuit application. This particular EVM configuration contains a single linear regulator for high-speed communication systems.
  • Page 3: Soldering Guidelines

    , and Maximum Power Dissipation Board Package θ Max Dissipation (T Max Dissipation @2A 25°C) = 70°C) TPS7A8300 High-K 35.7°C/W 2.80 W 1.54 W SLVU919 – June 2013 TPS7A8300EVM-209 Evaluation Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 4: Board Layout

    Board Layout www.ti.com Board Layout Figure 1 Figure 3 illustrate the PCB layout for this EVM. Figure 1. Assembly Layer Figure 2. Top Layer Routing TPS7A8300EVM-209 Evaluation Module SLVU919 – June 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 5: Bottom Layer Routing

    Board Layout www.ti.com Figure 3. Bottom Layer Routing SLVU919 – June 2013 TPS7A8300EVM-209 Evaluation Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 6: Schematic

    Schematic www.ti.com Schematic Figure 4 is the schematic for this EVM. Figure 4. TPS7A8300EVM-209 Schematic TPS7A8300EVM-209 Evaluation Module SLVU919 – June 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
  • Page 7: Bill Of Material

    Bill of Material www.ti.com Bill of Material The BOM for this EVM is shown in Table 2 Table 2. Table 2. TPS7A8300EVM-209 BOM RefDes Value Description Size Part Number C6, C7 0.01uF Capacitor, Ceramic Chip, GRM188R71H103KA01D Murata 50V, ±10%, X7R 1.0 uF...
  • Page 8 Any exceptions to this are strictly prohibited and unauthorized by Texas Instruments unless user has obtained appropriate experimental/development licenses from local regulatory authorities, which is responsibility of user including its acceptable authorization.
  • Page 9 FCC Interference Statement for Class B EVM devices This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications.
  • Page 10 Also, please do not transfer this product, unless you give the same notice above to the transferee. Please note that if you could not follow the instructions above, you will be subject to penalties of Radio Law of Japan. Texas Instruments Japan Limited (address) 24-1, Nishi-Shinjuku 6 chome, Shinjuku-ku, Tokyo, Japan http://www.tij.co.jp...
  • Page 11 FDA Class III or similar classification, then you must specifically notify TI of such intent and enter into a separate Assurance and Indemnity Agreement. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2013, Texas Instruments Incorporated...

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