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Pin 51 - Supply Voltage, Digital Circuitry VSUPD*
Pin 52 - Ground, Digital Circuitry GNDD*
Digital Circuitry Input Reference
Pin 53 - Main Clock Input LLC2(53)
This is the input for the line-locked clock signal. The fre-
quency can be 27, 32, or 40.5 MHz.
Pin 54...61 - Picture Bus Luma Y0...Y7
The Picture Bus Luma lines carry the digital luminance
data.
Pin 62 - Line-Locked Clock Input LLC1
This is the reference clock for the single frequency input
sync signals required in a FIFO application. The frequency
can be 13.5, 16, or 20.25 MHz.
Pin 63 - Sync Signal Input HS
This pin gets the horizontal sync information. Either single
or double horizontal frequency or VGA horizontal sync sig-
nal.
Pin 64 - Sync Signal Input VS
This pin gets the vertical sync informatoion. Either single
or double vertical frequency or VGA vertical sync signal.
All manuals and user guides at all-guides.com
Pin 65, 66 - Crystal Output / Input XTAL2 / XTAL1
These pins are connectecd to an 5-MHz crystal oscillator.
The security unit for the HOUT signal uses this clock sig-
nal as reference.
Pin 67 -
Via this pin the
the DDP 3310B.
Pin 68 -
Via this pin, the clock signal for the
plied. The signal can be pulled down by an internal tran-
sistor.
* Application Note :
All ground pins should be connected separeately with
short and low-resistive lines to a central power supply
ground. Accordingly, all supply pins should be connected
separately with short and low-resistive lines to the power
supply. Decoupling capacitors from VSUPP to GNDP,
VSUPD to GNDD, and VSUPO to GNDO are recom-
mended to be placed as closely as possible to the pins.
17
IC DESCRIPTION
2
I C
Data Input/Output SDA
2
- bus data are written to or read from
I C
2
I C
Clock Input SCL
I C
APPENDIX
2
-bus will be sup-
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