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Logic Page
Function or
Significant I/O Signals
Location and Name
Type
Reference
Major Units
Input
Output
*A2
9072
KMl11-161
Tests for mod ified
Keybd Strobe; Keybd
KB lock; FF Enable; Ld
Keyboard Controls - 2
characters and
Reset; CU Busy;
KB to Fets; Char Rdy
protected data.
Index; I/O Unlock
Decode; MDT Load Bit 7.
Contains keyboard
Keybd; Allow Char
operation latches,
Load.
control latches,
,
and MDT latch.
*B2
9069
KM011-071
Contains KB decoder,
KB Bits 1-7, and P;
KB Op Decoder outputs;
Keyboard Controls - 1
Tab controls, Cursor
Alpha Shift; NumeriC
Char Edit; Csr Edit;
Controls, and
Shift; KB Strobe.
Op Complete; I nsert Bit
Insert/Delete
9; Csr Move; Keybd Bits
Controls.
1-7.
C2
9066
MG011-061
Contains message
CR Bits0-9;SR
FQ Ser in Bits 0-9; Mesg
I/O Gating and Parity
buffer register and
Bits 3-11; KB Bits
Bfr Bits 1-9; Attb Reg
parity check
1-7; Fets Out Bits
Bits 2-6; P Chk Bfr.
circuits, late
0--9; Load I/O Data;
reg ister, attribute
Load Message Buffer.
register, and
gating circuitry
for line buffer and
message buffer.
02 (Modell)
9057
MB011-061
Modell - Contains
FQ Ser in Bits 0-9;
Fets Out Bits 0-9.
480 Storage and Gate
480-character
Serial Shift Gt;
message buffer
Shift Fets.
and gates.
02 (Model 2)
9065
MB011-061
Model 2 - Contains
TQ Ser in Bits 0-9.
960 Storage and Gate
960-character message
buffer and gates.
E2
L514
KA111-121
Contains line driver
Data to Control Unit;
Data to Control Unit;
SE R DES and Special
and line receiver,
Data to Driver
Data from Driver Receiver;
Circuits
I/O serializer/
Receiver; Mesg Bfr
SR Bits 1-12;Osc.
deserializer
Bits 1-9; Keyb bits
(SE ROES) and gates,
3-7; Data.
oscillator, and
5V relay switch.
F2
9065
MB111-161
Model 1 - Not used.
Third Quarter Serial
Fets Out Bits 0--9.
960 Storage and Gate
Model 2 - Contains
in Bits 0-9 (from
960 character
card 02); Shift Fets.
message buffer and
gates.
G2
9068
KA011-081
Contains operation
Osc, End Screen;
Stop Clock; Index; Sound
I/O Control
decoder, I/O gating
Fets Out Bit 7-8;
Alarm; Write Latch;
controls, status
SR Bits 1-12; Data
System Ready Latch;
register, SE ROES
from Driver Receiver;
Control Word
1
and 2;
controls, and cursor
Attention inputs.
Clock; Data; I nput Data;
positioning controls.
Device Busy; Read Sync;
Xmit Check; Read Out
Shift; Data to Driver
Receiver; CU Busy;
Input Inhibited; Load
I/O Data; Protected Bfr.
*OPtional feature cards
Diagram 6-8. Logic Card Data (Sheet 1 of 2)
6-10
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