Table of Contents
Advertisement
EtherLink/MC:
A
Register Definitions
A-1
Appendix A: Register Definitions
All
EtherLink/MC adapter registers are 8-bit registers. Word accesses to a register will result in two
accesses occurring to neighboring registers. 16-bit cycles are permitted.
Register 0: Network Address - byte 0 (Read Only)
7
6
5
4
3
2
1
0
47
46
45
44
43
42
41
40
I
I
~
I
~
I
~
I
~
I
Register 1: Network Address - byte 1 (Read Only)
7
6
5
4
3
2
1
0
39
38
37
:36
35
34
35
:32
i
I
~
I
~
I
e
Register 2: Network Address - byte 2 (Read Only)
7
6
5
4
3
2
1
0
i
31
~o
~
~8
=7
=s
~
=4
=
I
~
!
~
I
~
I
t
]
Network Address - byte 3 (Read Only)
6
5
.~
3
2
Register 3:
7
1
0
I
~
=
~
~o
~
~8
~
~s
~
I
~
I
~
I
~
I
~
I
Register 4: Network Address - byte 4 (Read Only)
7
6
5
4
3
2
1
0
15
14
13
12
11
10
9
8
~
I
~
I
~
I
~
Register
5:
7
Network Address - byte 5 (Read Only)
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
~
I
~
I
~
I
~
Advertisement
Table of Contents
