Parts - Pioneer VSX-AX5i-S Service Manual

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7.2 PARTS

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7.2.1 IC 3 7 63 1515 0
• The information shown in the list is basic information and may not correspond exactly to that shown in the schematic diagrams.
List of IC
PD8112A, PD5948A8, PD5899A, PD5771B, BU4094BCF
PD8112A (1394 ASSY: IC301)
• Flow Control IC
Pin Function
No. Pin Name
1 VDDOUT
2 SPDIFOUT
3 SDATA3O
4 SDATA2O
5 SDATA1O
6 SDATA0O
7 LRCKOUT
8 BCKOUT
9 AMCLKOUT
10 AMCLKEN
11 SDERRO
12 VSSOUT
13 VDDOUT
14 SDMUTEO
15 SAPCMBCKIN
16 SAPCMLRCKIN
17 SAPCMD3IN
18 SAPCMD2IN
19 SAPCMD1IN
TE
L 13942296513
20 SACDMKO
21 SACDDAO
22 SACDD0O
23 SACDD1O
24 SACDD2O
25 SACDD3O
26 VSSCORE
27 VDDCORE
28 SACDD4O
29 SACDD5O
30 SACDFRO
31 TESTMODE0
32 TESTMODE1
33 PLLMODE
34 SAPCMMODE
35 XVALMODE
36 RJMSBF
37 SEL512
38 CONT48
39 CLK48K
40 CLK48KI
41 CLK48KO
42 VSSOUT
43 VDDOUT
www
44 CONT44
45 CLK44K
46 CLK44KI
.
47 CLK44KO
48 SELOSC
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I/O
−
Digital VDD (3.3V)
O IEC60958 output
O MBLA data output (5 ch, 6 ch) (at flow: I2S)
O MBLA data output (3 ch, 4 ch) (at flow: I2S)
O MBLA data output (1 ch, 2 ch) (at flow: I2S)
O MBLA ancillary data output (at flow: I2S)
O MBLA LRCK output
O MBLA BCK output (64fs)
O Master clock output (When AMCLKEN output is LOW, active Hi-Z.)
O When 60958 is selected or OUTPUTEN=L output, active LOW. For external clock control
O Data error flag output
−
Digital GND
−
Digital VDD (3.3V)
O Data mute flag output
I BCK input when converting SACD to MLPCM
I LRCK input when converting SACD to MLPCM
I DATA3 input when converting SACD to MLPCM
I DATA2 input when converting SACD to MLPCM
I DATA1 input when converting SACD to MLPCM
O SACD master clock output (2.8224MHz)
O SACD ancillary data output
O SACD data output (L)
O SACD data output (R)
O SACD data output (C)
O SACD data output (Lfe)
−
Digital GND (for inside)
−
Digital VDD (3.3V, for inside)
O SACD data output (Ls)
O SACD data output (Rs)
O SACD frame data output (75Hz)
I LSI test mode input
I LSI test mode input
I VCOCLK division ratio selection
I 0: normal, 1: When the data type is SACD, output SAPCM*** input to MLPCM.
I 0: 64M•128M bit SDRAM, 1: 256M bit SDRAM
I MLPCM output format setting at flow
I Master clock selection at flow 0: 768fs, 1: 512fs
O Output for controlling the oscillator (When FMODE="1" and SEL44K="1", active High)
I Master clock input of fs48kHz (36.864MHz or 24.576MHz)
I Crystal resonator input of fs48kHz (24.576MHz)
O Crystal resonator output of fs48kHz (24.576MHz)
−
Digital GND
−
Digital VDD (3.3V)
O Output for controlling the oscillator (When FMODE="1" and SEL44K="0", active High)
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I Master clock input of fs44.1kHz (33.8688MHz or 22.5792MHz)
y
I Crystal resonator input of fs44.1kHz (22.5792MHz)
i
O Crystal resonator output of fs44.1kHz (22.5792MHz)
L: CLK4XK input selection, H: crystal resonator I/O selection As for the crystal resonator, less than
I
30MHz are insured.
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Pin Function
MUTE: H
Q Q
3 6 7 1 3 1 5
Normally, "L" fixed
Normally, "L" fixed
Normally, "L"
0: I2S, 1: Right aligned MSB first
co
.
VSX-AX5i-S
7
9 4 2 8
0 5 8 2 9 9 4 2 8
m
7
8
9 9
A
B
C
9 9
D
E
F
159
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