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2 is then in the last (or highest) addressing position and an inline
ripple (discussed below) can be performed on it.
If box 1 is the
malfunctioning box, a horizontal reversal of boxes 3, 5, and 1 with
boxes 4, 6, and 2, respectively, puts box 1 in the highest addressing
position.
(The ascending addressing sequence of the boxes is then
4-3, 6-5,
2-1.)
Storage Ripples
Five storage ripple functions are implemented in Model 165 hardware
as maintenance aids for use by customer engineers.
(A ripple is a
nonprogrammed read or write of ones or zeros through every available
storage address for the purpose of locating a malfunction.)
A ripple
is provided for ROS,
wes,
local storage, and processor storage that
requires dedication of the system to the ripple function.
However,
an inline processor storage ripple also is implemented.
It can be
executed on a malfunctioning storage box that has been configured out
of the operational system while processing continues.
(The processor
storage box must be in the highest addressing position.)
An inline
ripple is not provided for the Model 65, which therefore requires total
system unavailability during processor storage rippling.
In addition,
there is no reconfiguration capability for main storage boxes in
uniprocessor Model 65 systems.
HIGH-SPEED BUFFER STORAGE
The increase in the internal performance of the Model 165 is achieved
largely by the inclusion of a high-speed buffer storage unit.
The
8K buffer is a standard feature and provides high-speed data access
for CPU fetches.
Installation of the optional Buffer Expansion feature
permits inclusion of an additional 8K of buffer storage.
The buffer has an 80-nanosecond cycle.
The CPU can obtain eight
bytes from the buffer in two cycles, or 160 nanoseconds, and a request
can be initiated every cycle.
This compares with 1.44 microseconds
(or 18 cycles) required to obtain eight bytes of data directly from
processor storage.
The conceptual data flow in the Model 165 is
pictured in Figure 10.15.3.
Buffer storage control and use is handled entirely by hardware and
is transparent to the programmer, who need not adhere to any particular
program structure in order to obtain close to optimum use of the buffer.
The buffer algorithm implemented in the Model 165 is very similar to
that used in the System/360 Model 195.
Sample job step executions
have shown that in a Model 165 the data accessed by the CPU is in the
buffer
95~
of the time on the average.
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