IBM System/370 Manual page 25

Error checking and correction (ECC) hardware provides automatic
detection and correction of all single-bit processor storage errors
and detection, but not correction, of all double-bit and most multiple-
bit errors. The ECC feature is discussed fully in the RAS section.
The Model 165 also supports a byte boundary alignment facility for
processor storage. The presence of the byte-oriented operand function
allows the storage operands of unprivileged instructions (RX and RS
formats) to appear on any byte boundary without causing a specification
program interrupt. Without this facility, operands must be aligned
on integral boundaries, that is, on storage addresses that are integral
multiples of operand l~ngths. Byte orientation is standard and does
not apply to alignment of instructions or channel command words (CCW's).
Use of byte alignment in a program degrades instruction execution
performance. However, byte orientation can be used effectively in
commercial processing to eliminate the padding bytes added within
records and to blocked records to insure binary and floating-point
field alignment. The smaller physical record that results from the
elimination of padding bytes requires less external storage and
increases effective I/O data rates. I/O-bound commercial programs,
in which throughput is in almost direct proportion to the I/O data
rate, can achieve performance improvement by using byte alignment for
binary and floating-point data.
A program written to use byte boundary alignment will not necessarily
run on a System/360 model that does not have the feature. Therefore,
programs that are to run on both the Model 165 and on System/360 models
without byte orientation should be written to adhere to integral
boundary rules.
Processor Storage Reconfiguration
If a processor storage box develops a malfunction, it can be
configured out of the system by use of the storage configuration
plugboard in the system console. Then the operating system can be
re-IPLed and the system can continue operating with reduced available
storage. The configuration indicated by the plugboard is established
during a power-on sequence or a system reset operation.
The user has the ability to remove one or more storage boxes from
the operative system and reconfigure the addressing of the remaining
boxes to achieve consecutive storage addressing. Interleaving is
reduced from four-way to two-way if the configuration consists of an
odd number of boxes. Therefore, four-way interleaving can be maintained
in systems with four or six processor storage boxes by removing a pair
of boxes instead of the malfunctioning box only. A pair must be removed
in a 3072K (six-box) system as a 2560K configuration is not supported.
Serial operation is possible also and will be used primarily by customer
engineers.
The configuration panel is relatively simple to use. The operator
inserts plugs into the appropriate holes in the panel to describe the
processor storage configuration: number of boxes (one to six) using
up to three plugs, box addressing sequence (box reversals) using up
to two plugs, and interleaving (four-way, two-way, or serial) using
up to two plugs.
With the few reversal combinations defined, any box can be placed
in the first or last box addressing position. Assume box 2 in a six-
box configuration is to be configured out of the operational system.
(Refer to Figure 10.15.1, in which box numbers also indicate the
sequential positioning o~ consecutive processor storage box addressing.)
Boxes 1 and 2 would be vertically reversed in position with boxes 3
and 4, respectively, and then with boxes 5 and 6, respectively. Box
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