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memory.
~.
W[,
are
the read and write
signaLs for strobing
data onto the bus.
TO
is a feedback signaL from the keyboard indicating
whether
a
particuLar key is being depressed.
It is an active high signaL.
T1
is a status signaL randomLy monitored by the processor.
this signal is inserted,
it indicates that a character has
received
by
the
UART (88) and is ready to be fetched
by
processor.
When
been
the
!NT
is an interrupt request signaL asserted by the CRT controLLer
(78) when screen refresh is required.
The processor responds to
the interrupt request by initiating a DMA process which transfers
a bLock of 80 characters from the display RAM (6A-13A) to the CRT
controLlers (78, 88).
RESET
input
signal
provides
a
means
for
initializing
the
processor upon power-on.
It is held at logic low for at least 30
milliseconds after the power supply is in tolerance.
3.1.2
DispLay Memory (6A-13A)
The
dispLay
memory consists of
2K (4K) bytes
of
memory,
or
4 (8)
2114 1K x 4 static memory components (6A-13A) external
to
the
processor.
It is accessed by the processor to refresh
the
screen
and
to
update the text.
The lower address
lines
are
Latched
by an 8-bit Latch (3A) on the rising edge of ALE
during
each external memory cycLe.
A two-to-four decoder (58) is
used
to
decode
the
upper address Lines A10 and A11 into a
1K
byte
memory bLock, and to select a pair of 2114 memory components.
3.1.3
Program Memory
(28/38)
The terminal program is stored in a 4K x 8
2732 (28) EPROM.
It
contains
the display driver,
the communication interface
firm-
ware
and the keyboard scanner.
AlternativeLy,
the 2732 can
be
substituted
with two
2716s (28,
38) by slightly modifying the
control line VPP/A11 and address line CEo
3.1.4
Communications and Data 8uffer
A 1K byte
buffer consists of two 2114 static memory chips
(4A,
5A)
used
as a buffer RAM area for storing
characters
received
from
communication ports,
soft function key codes and
descrip-
tions on the
screen.
This 1K memory address space overlaps the
4K display RAM area.
The
I/O port P24 of 8039 is used to select
either the buffer RAM or display RAM access.
Logic board module 1-7
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