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The
logic board is functionally divided into four parts:
micro-
processor controller,
video timing, communication interface, and
keyboard interface. See Figure 1 for a block diagram of the Logic
board.
3.1
MICROPROCESSOR CONTROLLER
The microprocessor controller consists of an 8039
microcomputer,
display
and
buffer
memory,
program memory,
I/O
and
address
decoder, and support
circuits that are connected directly to the
processor bus.
(See Figure 2 for the timing diagrams and
Figure
A-1 for the schematic).
3.1.1
8039 Microcomputer (98)
The
8039 microcomputer is an 8-bit microprocessor with 128 bytes
of
internal
RAM,
two
8-bit I/O ports and
an
on-chip
timer/
counter.
It
operates with a 10.376 MHz crystal (X1)
which
is
also
used
for
baud rate generation in the
data
communication
interface section,
resulting in a 1.48 microsecond
instruction
time for one-cycle instructions.
The data bus lines DBO through DB7 are used for transfer
tions
and data bytes bet wen 8039 (98) and program
ROM
display and buffer
RAM
(4A-13A),
CRT controllers (7B,
UART
(48).
They
are
multiplexed into
address
lines
instruction fetch and external memory access.
instruc-
(2B/3B),
88) and
during
I/O
ports P10 through P16 are used for outputting row and column
addresses during keyboard scan.
P17 is a beLL enable signal.
It
is used by the microprocessor to sound the bell.
It is also used
to provide an audio feedback effect to the keyboard by generating
a click when a key is pressed on the keypoard.
The
second
I/O
port
is
used
for
I/O
and
memory
devices
selection.
The
lower four lines P20-P23 also contains the four
high order bits of address A8-A11 during external memory
access.
In device selection mode,
P20 indicates whether the data byte on
the
bus
is
a
command or a data byte when
accessing
the
CRT
controllers.
In memory selection mode,
P20 contains the address
bit
A8.
P21-P23 contain the address bits A9-A11,
respectively;
and they are meaningful
onLy in the memory seLection mode.
P24
seLects
either the display RAM (6A-13A) or buffer RAM
(4A,
SA)
for externaL RAM access.
P2S enabLes the read/write operation of
the
UART.
P27
selects
the
output
data
from
UART
to
be
transmitted
through
either the RS-232 modem port
(J1)
or
the
serial printer port (J2).
ACE, PSIN,
[0,
and WR are output controL signaLs.
AtE
is a cLock
signaL
used
to Latch the address bits during a memory
or
I/O
cycLe.
PSEN
occurs
onLy during a fetch
to
externaL
program
logic board module 1-4
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