Sdram - Harman Kardon AVR 151/230C Service Manual

Harman Kardon
ESMT

SDRAM

FEATURES
JEDEC standard 3.3V power supply
LVTTL compatible with multiplexed address
Dual banks operation
MRS cycle with address key programs
- CAS Latency (2 & 3 )
- Burst Length (1, 2, 4, 8 & full page)
- Burst Type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the
system clock
Burst Read Single-bit Write operation
DQM for masking
Auto & self refresh
32ms refresh period (2K cycle)
PIN CONFIGURATION (TOP VIEW)
Elite Semiconductor Memory Technology Inc.
(Preliminary)
GENERAL DESCRIPTION
ORDERING INFORMATION
M12L16161A-5TG2Q
M12L16161A-7TG2Q
(TSOPII 50L, 400milX825mil Body, 0.8mm Pin Pitch )
V 1
DD
DQ0 2
DQ1 3
V 4
SSQ
DQ2 5
DQ3 6
V 7
DDQ
DQ4 8
DQ5 9
V 10
SSQ
DQ6 11
DQ7 12
V 13
DDQ
LDQM 14
WE 15
CAS 16
RAS 17
CS 18
BA 19
A10/AP 20
A0 21
A1 22
A2 23
A3 24
V 25
DD
M12L16161A (2Q)
512K x 16Bit x 2Banks
Synchronous DRAM
The M12L16161A is 16,777,216 bits synchronous high data
rate Dynamic RAM organized as 2 x 524,288 words by 16 bits,
fabricated with high performance
Synchronous design allows precise cycle control with the use
of system clock I/O transactions are possible on every clock
cycle. Range of operating frequencies, programmable burst
length and programmable latencies allow the same device to
be useful for a variety of high bandwidth, high performance
memory system applications.
Product ID Max Freq.
200MHz
143MHz
V
50
SS
49 DQ15
48 DQ14
47 V
SSQ
46 DQ13
45 DQ12
V
44
DDQ
DQ11
43
DQ10
42
V
41
SSQ
DQ9
40
DQ8
39
V
38
DDQ
N.C/RFU
37
UDQM
36
35 CLK
34 CKE
33 N.C
32 A9
31 A8
30 A7
A6
29
A5
28
A4
27 50PIN TSOP(II)
(400mil x 825mil)
V
26
SS
(0.8 mm PIN PITCH)
Publication Date : Mar. 2011
Revision : 0.1
AVR 151 Service Manual
CMOS technology.
Package Comments
TSOP(II) Pb-free
TSOP(II) Pb-free
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