Sony CXD5602 User Manual page 951

3.14.3.6.2 Register Descriptions
The reset of each block can be controlled using the registers. Since the control flow varies according to the
function block, refer to each block's Section. Table SYSIOP Clock and Reset Control-809 shows the reset control
registers.
Table SYSIOP Clock and Reset Control-769 Reset Control Registers
Address Register
0x04100700 SWRESET_BUS
Bit Field Name Type
Reserved RO
XRST_PMU_I2C RW
M
Reserved RO
XRST_I2CM_SU RW
B
XRST_UART0 RW
XRST_HOSTIFC RW
_ISOP
XRST_HOSTIFC RW
Reserved RO
XRST_UART1 RW
Reserved RO
XRST_SAKE RW
－951/1010－
Bit Initial Description
Value
[31:17] 0 Reserved
[16] 1
Indicated as RST(9) in
Clock and Reset Control-117
Reset for I2C4
0 Reset is performed
1: Reset release
[15:12] 0 Reserved
[11] 0 Indicated as RST(8) in
Clock and Reset Control-117
Reset for I2C2
[10] 0 Indicated as RST(7) in
Clock and Reset Control-117
Reset for UART0
[9] 0 Indicated as RST(6) in
Clock and Reset Control-117
Reset for HOSTIFC Sequencer
[8] 0
Indicated as RST(5) in
Clock and Reset Control-117
Reset for HOSTIFC
[7:6] 0 Reserved
[5] 0
Indicated as RST(3) in
Clock and Reset Control-117
Reset for UART1
[4:3] 0 Reserved
[2] 0
Indicated as RST(2) in
Clock and Reset Control-117
Reset for Crypto(Clefia)
CXD5602 User Manual
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