Sony CXD5602 User Manual page 930

3.13.4.16.5 Reset Assert and Release
Control Reset Enable and Release using System and I/O Processor or ADSP other than the target ADSP processor.
Note: about <N>
E.g., ADSP0 means that N = 0, ADSP1 means that N = 1, in the same way, ADSP5 means that N = 5.
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Precondition
The ADSP must be in SLEEPING state so that uncompleted accesses will not remain in buses. (Refer to
the PMU chapter 3.4 and 3.13.4.9 section.)
1. Reset assert
RESET.xrs_dsp<N>=0
2. Clock stop
CK_GATE_AHB.ck_gate_dsp<N>=0
3. Reset release
RESET.xrs_dsp<N>=1
4. Clock supply
CK_GATE_AHB.ck_gate_dsp<N>=1
3.13.4.16.6 ADSP Stop
Control ADSP stop using System and I/O Processor or ADSP other than the target ADSP.
Note: about <N>
E.g., ADSP0 means that N = 0, ADSP1 means that N = 1, in the same way, ADSP5 means that N = 5.
Precondition
The ADSP must be in SLEEPING state so that uncompleted accesses will not remain in buses. (Refer to the PMU
chapter 3.4 and 3.13.4.9 section.)
1. Reset assert
RESET.xrs_dsp<N>=0
2. Clock stop
CK_GATE_AHB.ck_gate_dsp<N>=0
3.13.4.16.7 PWD_APP_DSP Power Supply OFF
For power supply control, refer to the PMU chapter 3.4.
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CXD5602 User Manual