Dell 1907FPf Service Manual page 19

53 VSS
54 VDD18
55 VSS
56 NC
57 XTAL2
58 XTAL/CLKIN
59 CFG/-SEL2
60 VDDA18PLL
61 VDDA33PLL
62 ATEST/REG_EN
63 RBLAS
64 VSS
12
.3 U850 (SG6841, PWM Power Controller)
Pin Symbol
1 GND
2 FB
3 VIN
4 RI
5 RT
6 SENSE
7 VDD
8 GATE
12.4 U1 (OZ9936G, CCFL Inverter controller IC)
Pin Symbol
1 SST_CMP
2 CT
3 GNDA
4 DRV2
5 DRV1
6 VDDA
7 VSEN_DIM
8 ISEN
monitors VBUS_DET to determine when to assert the internal
D+ pull- up resistor.
Ground
+1.8V core power
Ground
Not connected
OCLKx 24MHz crystal
This is the other terminal of the crystal, or left unconnected when
an external clock source is used to drive XTAL1/CLKIN.
24MHz crystal or external clock input.
I This pin is read on the rising edge of RESET_N negation and
will determine the hub configuration method.
+1.8V Filtered analog power for internal PLL.
+3.3V Filtered analog power for the internal PLL
AIO This signal is used for testing. The analog section of the chip,
and to enable or disable the internal 1.8v regulator.
I-R A 12.0kohm (+/-1%) resistor is attached from ground to this pin
to set the transceiver' s internal bias settings.
Ground
I/O
Ground
I Feedback, the FB pin provides the info rmation of
the regulation. The PWM duty cycle is controlled by
FB
I Start-up current input
I Reference setting, typical voltage 1.3V
N.C.(not connected)
I Current sense for over current protection
I Power supply
O PWM output
I/O
I Enable, soft start time and compensation of current
error amplifier
I Timing capacitor to set operating frequency
Ground
O N MOSFET Driver output
O N MOSFET Driver output
I Supply voltage input
I Voltage sense, input analog signal for PWM driving
control
I Lamp current detection & control
18
Service Manual
Description
Description