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Circuit Descriptions, Abbreviation List, and IC Data Sheets
9.4.5
Diagram B5A, SVP_PX66LX66
Block Diagram
SVP™PX66
3 CVBS
2 Chroma
PC RGB x 1
(up to SXGA 60Hz)
Ypbpr x 2 (D1/D2/D3/D4)
2FB & 2 FS (SCART)
(24 + 8) bit in
(8/16) bit in or (8 bit in, 8bit out)
HDMI/DVI Signals In
Pin Configuration
1
2
3
MD27
MD26
MD25
MD23
A
DQM3
DQS3
VSS
VDDM
B
C
MD28
MD29
MD30
VDDM
D
MCK0
VSS
MD31
VDDM
MCK0#
VDDR
MVREF
E
VSSR
F
MA11
MA10
MA9
MA8
G
MA4
MA5
MA6
MA7
H
MA3
MA2
MA1
MA0
C
A
S
#
R
A
S
#
C
S
# 1
C
J
WE#
CLKE
BA0
BA1
K
TMDS_G
L
RXC+
RXC-
PVCC
ND
TMDS_G
M
RX0+
RX0-
AVCC
ND
TMDS_G
RX1+
RX1-
AVCC
N
ND
TMDS_G
P
RX2+
RX2-
AVCC
ND
TMDS_G
AVDDLL
R
PAVSS2
PLF2
ND
PLL
AVSSLLP
T
LL
PAVSS1 PAVDD1 PAVDD2
AVDDAP
AVDD3_
U
MLF1
FB2
LL
OUTBUF
AVSSAP
CVBS_O
AVDD3_
V
LL
FS1
UT2
BG_ASS
CVBS_O
AVSS_B
W
XTALI
FS2
UT1
G_ASS
XTALO AVSS_O
AVDD3_
Y
CVBS1
UTBUF
ADC1
1
2
3
UMAC
Memory Control
ADC
3D Video
108
Decoder
Mhz
ASS/DSS
108Mhz
VBI
Din_portA
Slicer
(32 bit) Input
108Mhz Din_portB
(16 bit) Input/Output
HDMI/HDCP
MCU
RX
Interface
8/16 bit
CPU bus
Flash
CPU
ROM
4
5
6
7
8
MD21
DQM2
MD19
MD12
DQM1
MD22
DQS2
MD18
MD13
DQS1
MD24
VSS
MD17
MD14
VDDM
MD20
MD16
MD15
MD11
VDDM
VSSR
VDDM
VDDM
VDDR
VDDM
VDDM
VDDC
V
S
S
S
# 0
V
D
D
C
V
S
S
VSS
VDDC
VSS
V
S
S
ANTSTO
VSS
VSS
AVCC
DGND
REGVC
C
AVSS_A
AVSS_AD
AVSS_AD
AVDD_AD
AVSS_AD
C4
C2
C3
DC1
AVDD_A
AVDD_AD
AVDD_AD
AVDD3_A
PC_R
C4
C2
DC1
VREFN_
Y_G1
VREFN_2
PR_R3
1
VREFP_
Y_G2
VREFP_2
PR_R2
PB_B1
1
FB1
Y_G3
PC_G
PR_R1
PB_B2
4
5
6
7
8
Figure 9-7 Internal block diagram and pin configuration
DDR/SDR
32 bit DDR
MP
CRTC
Noise
Reduction
10bit Gama
MP
MP
LCD Over
6
3D motion
Drive
Generation
Deinterlacer
Scaler
CSC
PIP
PIP
White
Deinterlacer
Scaler
Balance
MP
Color
ICSC
Sharpness
Management
Control
MP
OSD
Dynamic
Engine
Contrast
GPIO
I2C
PWM
GPIO
I2C
9
10
11
12
13
MD7
MD6
DQM0
MD2
MD8
MD5
MD1
DQS0
VSS
MD9
MD4
VSS
MD0
VDDM
VDDC
MD10
MD3
VDDM
VDDM
VDDM
VDDC
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
VSS
VSS
VSS
VSS
VSS
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
PWR5V
DSCL
VDDH
VDDH
C3
AIN_VS
DSDA
WS
DPA_22
DC2
C
AIN_HS
SCDT
SD0
DPA_21
AUDIOCL
PC_B
SPDIF
DPA_20
K
PB_B3
SCK
DPA_23
DPA_19
9
10
11
12
13
TPT1.1HA LA
9.
PCLK/H/V
Panel
Timing
Single 8bit/10bit LVDS
Channel (1366x768P
Single Channel
Output)
10-bit LVDS Tx
(85Mhz per
channel)
I2S & SPDIF
I2S &
SPDIF
CVBS Out x 2/
Svideo_out
CVBS_OUT
2 x PWM
14
15
16
17
18
TA1P
TB1P
TC1P
TCLK1P
TD1P
TC1M
TD1M
TA1M
TB1M
TCLK1M
LVDS_V
LVDS_VD
LVDS_VSS
VDDC
VDDC
DO
SSD
O
LVDS_V
LVDS_VD
LVDS_VD
VDDC
VDDC
DDD
DP
DO
LVDS_V
LVDS_VD
LVDS_VSS
VDDC
SSA
DA
P
VDDC
TESTMOD
V5SF
RESET
E
VDDC
PWM0
INTN
V
D
D
C
S
D
A
S
C
L
V
D
D
C
C
P
U
_
C
S
A
L
E
AD4
AD5
VDDC
V
D
D
H
A
D
0
A
D
1
VDDH
ADDR7
ADDR6
VDDH
ADDR0
ADDR1
VDDH
VS
VSS
VDDC
Rsvd
Rsvd
VDDC
VDDC
VSS
DPB_10
DPB_11
DPA_15
DPA_14
DPA_8
DPA_7
DPB_15
DPA_16
DPA_13
DPA_9
DPA_6
DPA_1
DPA_17
DPA_12
DPA_10
DPA_5
DPA_2
DPA_18
DPA_CLK DPA_11
DPA_4
DPA_3
14
15
16
17
18
EN 71
19
20
TE1P
Revd
A
TE1M
Revd
B
LVDS_VSS
Revd
C
O
Rsvd
Rsvd
D
Rsvd
Rsvd
E
Rsvd
Rsvd
F
Rsvd
Rsvd
G
R
s
d v
R
s
d v
H
W
R
#
R
D
#
J
AD6
AD7
K
A
D
2
A
D
3
L
ADDR5
ADDR4
M
ADDR2
ADDR3
N
HS
Rsvd
P
DPB_9
DPB_8
R
DPB_CLK
DPB_12
T
DPB_14
DPB_13
U
DPB_HS
DPB_VS
V
DPA_0
DPB_DE
W
DPA_HS
DPA_VS
Y
19
20
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