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Model 5065A
Circuit Diagrams, Theory, and Maintenance
DELAY thumbwheel switch S1A through S1F. This ad
justs the divider output phase from 1 jusec to 1 sec. The
phase adjustable output pulse is a 1 PPS, 1 yusec, "L"
signal at 9's detector NAND gate A3IC12A(6), applied
to inverter A3Q6 and gate around one-shot A3IC13(9).
The relationship between the 1 MHz input, the master
clock 1 PPS output, and the preset clock 1 PPS, 1 Msec,
output "L" pulse can be seen in A5 Digital Divider
Timing Diagrams.
The standard decade divider provides one output pulse
for each 10 input pulses. Preset divider A3IC3 provides
an output pulse through NAND gate A3IC9 to 9's de
tector A3IC12A(5) and to the following decade when
the preset count plus the input count total "9" (input to
following stage occurs at "8" and continues through
"9"). Operation of A3IC3 is the same as that shown in
the timing diagram for A2IC6 decade.
When the decade count is "0", all binary outputs are
"H" but as the count progresses, levels at pins 6, 7, 8,
and 1 change state depending on the number of pulses
into the decade. At the count of "9", pins 1 and 6 are
"L" (representing "9") and pins 7 and 8 are " H " . The
next input pulse "10" will cycle the decade to "0" and
the count begins again.
To change the decade to a divide-by-2 divider; when the
decade state is "0" (pins 6, 7, 8, 1 "H") and before any
input signal is applied to pin 5, pulses are applied to
pins 6, 7, and 8 driving them "L". The decade state is
now "7" before any input signal is applied. The first 2
input pulses cause pins 6 and 1 to go "L" and a "9" is
sensed at the output IC9A(3, 5). Thus, with only two
inputs there is an output or divide-by-2 action.
The preset clock divider chain may be set to divide by
any integer from 1 to 10
6
by setting the complement 9
into the decades prior to the counting sequence. This is
done automatically by TIME DELAY thumbwheel switch
S1A through F.
Whatever time delay is set on the
switch, the complement "9" is set into the preset clock
dividers prior to counting.
Assume a 1 fisec delay is set on the thumbwheel switch;
this presets 999998 into the dividers (switch setting is
000001).
When the master clock has completed its
counting sequence, the master tick output triggers the
reset and preset circuits in the preset divider section.
During reset and preset time, preset divider decade
inputs are held closed. During preset time, 999998 is
set into the decades via the thumbwheel switch and " H "
signals are preset at A3IC12A(2, 3, 1, 4). However, this
gate will not change state since an "L" is present from
A3IC9A(6) (this decade has the count of "8").
The first decade receives the first count pulse causing
A3IC9A(6) to go " H " which causes A3IC12A(6) to go "L"
until the next input pulse to A3IC1A(13) which arrives
1 ^sec later. The 1 sec "L" signal is inverted by A3Q6
and applied as an " H " pulse to NAND gate A3IC2(2).
The next gated 1 MHz output pulse from A2IC2 will also
8-30
place an " H " signal at A3IC2C(1).
This causes gate
A3IC2C to change state and apply an " H " signal
through NOR gate A3IC2D to the 0-1 /isec variable delay
s
-
mV on A5A4 Switch Board Assembly.
If a delay of 2 ^sec is desired, the sequence of events is
the same except 999997 would be the preset input in
formation.
Instead of the first pulse into A3IC3(5)
causing A3IC12A to change state, the second pulse —
causes the state change; thus, the pulse applied to the
0-1 jusec delay MV on A5A4 circuit board is changed in
phase by an additional microsecond. This same sequ
ence of events occurs for all switch settings except
999999.
When 999999 (note the A5 timing diagram) is set on the _
thumbwheel switch, no preset information is set into the
dividers and they divide by 10
6
. When this occurs, the
preset clock and master clock are dividing by the same
number. The dividers reach a count of 999999 and a —
small pulse is produced at A3IC12A(6). This pulse trig
gers gate around one-shot A3IC13, producing an " H "
1.1 jusec pulse that is applied to A3IC12B(12). When the
master tick goes "L", A3IC12A(6) goes " H " and A3IC15 ~
reset one-shot is triggered.
This places another " H "
pulse at NAND gate A3IC12B(10). With two of the re
quired three inputs present, the next gated 1 MHz pulse _
will gate through A3IC12B(9) and NOR gate IC2D to the
output circuits.
The 1 PPS output at A3IC2D(6) connects to A5A4 Switch
Circuit Board and is processed by variable delay one-
shot MV A4IC1 for a 0-1 /jsec time delay. This screw
driver adjustment provides continuous control over the —
0-1 ^sec period. The delayed output pulse connects from
amplifier inverter A4Q1 to the "tick" blocking oscil
lator in the A16 Digital Divider Power Supply module
which delivers the 1 PPS "tick" pulse to the front p a n e l "
jack.
For the clock-drive output, A3IC2D(6) 1 PPS output is
amplified by A3Q13, A3Q14, and A3Q15, and routed to
the clock drive amplifier on A16 Digital Divider Power
Supply.
When the STOP pushbutton is depressed,—
A3Q15 clock drive output is grounded to stop the front
panel clock. When the FAST pushbutton is depressed,
preset divider A3IC8 input pulses are routed through
A5S1 to A3Q14 for a 10 PPS clock drive output. This—
speeds up the front panel clock to advance it.
The 1 PPS output is synchronized to an external p u l s e "
by pressing SYNC pushbutton A5S2. This allows the
external pulse feeding in from SYNC jack A5J5 to trigger
one-shot MV A2IC1, resetting the master clock through_
A2Q5 to "0" and holding the input to gated 1 MHz one-
shot mV A2IC1 off for 7.3/usec. At the end of the 7.3/isec
period, the counting sequence will start.
Resistoi
A2R16 and capacitor A2C10 are adjusted for the 7.£_
lisec period.
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