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Model 5065A
Circuit Diagrams, Theory, and Maintenance
IC4 to "0" which then applies a count pulse to IC7(5),
cycling it to "0".
IC5 then applies a count pulse to
IC10(5), cycling it to "0". The decades are all reset
to "0" awaiting another counting sequence.
However,
the preset information has not been set into the decades.
decades in the preset divider.
Positive supply volt
ages for decades IC2, IC4, IC7, and IC10 connect to pin
3 and the negative supply voltages to pin 4.
Other
voltages are applied as follows:
The end of the 1.5 ^sec reset pulse triggers preset one-
shot multivibrator IC8. IC8 output is a 0.5 yusec pulse
applied at S1A, Q5, Q10, Q15, and NOR gate Q13, Q14.
This NOR gate signal continues to hold the input gate
closed for the length of the 0.5 ^isec preset pulse. The
total input gate close time is 2.0 jusec. This is the total
time required to reset and preset the decades. The 0.5
H sec pulse at S1A, Q5, Q10, and Q15 is applied to the
corresponding thumbwheel switch section.
Dependent
on switch setting, this pulse presets a count into the
decades. At the end of the 0.5 ,usec preset pulse, input
gate Q1, Q2 is open and the dividing function repeats.
a.
Decade IC10 connects between +20 V at R44-
R36and+13.3VatCR14.
b.
Decade IC7 connects between +13.3 V at
CR14and+9.1 VatCR7.
c.
Decade IC4 connects between +9.1 V at CR7
and +4.1 V at CR2.
d.
Decade IC2 connects between 4.2 V at CR2
and power ground.
POWER SUPPLY CIRCUITS
In addition to +20 V supplied to the Synthesizer, regu
lated 5.6 V is furnished by zener diode CR1. A special
power supply arrangement is provided for the counting
This decade power supply arrangement creates different
output drive levels. The drive levels are equalized by
the biasing action of zener diodes CR8, CR20, and CR25
working with Q7, Q8, and Q11, respectively.
Synthesizer Assembly A1 Timing Diagram
(fo.ooo)
I C 2 ( 5 )
INPUT
IC5 (6)
OUTPUT
IC5
INPUT
INT COUNT
ICII(7,I0)
RESET
IC8(IO)
PRESET
9999
I
J U U l
13
14 9999 10,000
f;5MHz
I
(9990)
|
|
9987 9988 9989 0
0
0
0
0
0
O
O
O
O
i
l
2 9987 9988
jmrLrumnjmjmJUXTLnvnJij
INPUT GATE
Ql AND Q2
PRESET DIVIDER COUNTING SEQUENCE THUMBWHEEL SET TO 0 0 0 0
7-16
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