Panasonic KX-TDE200GR Service Manual page 9

(1)
(2)
(3)
(4)
(5)
(6)
(7)
MAIN No.4
FPGA+RTC+SVM
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
(18)
(19)
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MAIN No.7
(49)
RS232_nDCD2 CLK_SD_33.33MHz
(50)
RS232_nDSR2
SD0_nRESET_SOFT
(51)
RS232_nDTR2
RS232_DCD2_CON
(52)
RS232_RXD2
(53) RS232_DSR2_CON
RS232_TXD2
RS232_DTR2_CON
(54)
RS232_nCTS2
RS232_RXD2_CON
(55)
RS232_nRTS2
RS232_TXD2_CON
RS232_CTS2_CON
(56)
SD0_CD
RS232_RTS2_CON
(57)
SD0_WP
(58)
SD0_nDRQ
(59)
SD0_DACK
SD&RS232
(60)
MCCLK
(61)
MCDAT
(62)
MCCMD
(63)
(64)
(65)
CLK_32.768kHz
(66)
CLKIO_66.66MHZ
(67)
nLOS_FPGA
nHALT_FPGA
RINGER_SYNC_FPGA
nBATT_FPGA
DC_ALM_FPGA
AC_ALM_FPGA
nFAN_ALM_FPGA
SHELF_nFAN_ALM_FPGA
LED_RUN_FPGA_DRIVE
LED_ALM_FPGA_DRIVE
CT_D[0]
CT_C8
CT_FRAME
SVM_DSP_OUT[1]
SVM_DSP_OUT[0]
HWFH_NEXUS
LUHW0_NEXUS
LDHW0_NEXUS
HW_CLK0_NEXUS
CH_SEL[5]
CH_SEL[6]
CH_SEL[7]
RMT_nRESET_SOFT
NEXUS_nRESET_SOFT
CL3146 nBUSY
RTC_nINT
CL3207
+3.3VD
+3.3VD
+3.3VD
DG
DG
DG
CL3203
CL3204
CL3157
CL3158
CL3159
CL3160
CL3161
VOX[0-3]
MELODYSEL
MOHSEL
SRAM_nWR
Mu/nA
SRAM_nBC1
SRAM_nBC0
EC_AD[0-15]
SRAM_nCS
MEMORY_CARD_PRESNT EC_PAR
EC_nCBE1
RMT_nRESET_SOFT EC_nCBE0
nRESET_SOFT EC_nFRAME
CLK_NEXUS_66MHz EC_nPERR
EX2_A[0-21]
EX2_D[0-15] EC_nSTOP
EX2_nDR EC_nTRDY
nWE1
EC_CLK
nWE0
EC_nCDET
nBS
EC_nINT
nBUSY
CT_D[0-7]
CT_NETAEF
nCS_NEXUS
CT_C8
nCS_SRAM
MAIN No.8
CT_FRAME
EXT_nINT0
RINGER
NEXUS(+SRAM)
MASTER/nS
nBACK
M/nS
nBREQ
POWER_TYPE1
NEXUS_nINT
POWER_TYPE0
nRESET_POWER
+3.3VD_B
DG
+3.3VD
+3.3VD
nBAT_ALM
TP_DRAM_VREF
KX-TDE200GR IPCMPR CARD DETAILED BLOCK DIAGRAM (2/2)
9
nLOS_FPGA
CL3190
CL3191 nHALT_FPGA
CL3192 RINGER_SYNC_FPGA
nBATT_FPGA
CL3193
DC_ALM_FPGA
CL3194
AC_ALM_FPGA
CL3195
nFAN_ALM_FPGA
CL3196
CL3197 SHELF_FAN_ALM_FPGA
LED_RUN_FPGA_DRIVE
CL3198
LED_ALM_FPGA_DRIVE
CL3199
SVM_VOX
MAIN No.15
+15V
SVM_DSP_OUT[1]
SVM_DSP_OUT[1]
SVM_DSP_OUT[0]
+15V
SVM_DSP_OUT[0]
+15V
+3.3VD
HWCLK[0]
LDHW[0]
+3.3VD
+3.3VD
CH_SEL[6]
DG
CH_SEL[7]
VOX[0-3]
DG
VOX[0-3]
Mu/nA
VREF_7.5V
DG
VREF_7.5V
CODEC
MAIN No.9
+15V
HW_CLK[0]
VREF_7.5V
HWCLK[0]
LDHW[0]
LDHW[0] +15V
LUHW[0]
LUHW[0]
+15V
CH_SEL[1]
CH_SEL[1] +3.3VD
CH_SEL[0]
CH_SEL[0]
+3.3VD
+3.3VD
CL3162
DG
MELODYSEL
MELODYSEL DG
CL3163 MOHSEL
MOHSEL
CL3164
Mu/nA
Mu/nA
DG
EC_AD[0-15]
EC_PAR
CL3165
EC_nCBE1
CL3166
CL3167 EC_nCBE0
EC_nFRAME
CL3168
EC_nPERR
CL3169
EC_nSTOP
CL3170
CL3171 EC_nTRDY
EC_CLK
CL3172
EC_nCDET
CL3173
CL3174 EC_nINT
CT_D[0-7]
CT_NETAEF
CL3175
CT_C8
CL3176
CL3177 CT_FRAME
CL3178 RINGER
MASTER/nS
CL3179
M/nS
CL3180
POWER_TYPE1
CL3181
POWER_TYPE0
CL3182
RS232_DCD2_CON
CL3183
RS232_DSR2_CON
CL3184
CL3185 RS232_DTR2_CON
RS232_RXD2_CON
CL3186
RS232_TXD2_CON
CL3187
RS232_CTS2_CON
CL3188
RS232_RTS2_CON
CL3189
+15V_CON TP_+15V_CON
+3.3VD_BB TP_+3.3VD_BB
+3.3VD
+3.3VD
+15V
DG
TP_+15V
+3.3VD_B
TP_+3.3VD_B
+3.3VD
POWER
+15V
TP_+3.3VD
+15V
+15V_CON
+3.3VD_B
+3.3VD_B
+3.3VD_BB
+3.3VD
+3.3VD
+2.5VD
nBAT_ALM +2.5VD
+1.8VD
nRESET_POWER
HARD_nRESET_SW +1.25VD
+1.2VD
DRAM_VREF
DG
MAIN No.13
DG
KX-TDE200GR
MAIN No.10
nLOS_FPGA
nHALT_FPGA
RINGER_SYNC_FPGA
nBATT_FPGA
DC_ALM_FPGA
AC_ALM_FPGA
nFAN_ALM_FPGA
SHELF_nFAN_ALM_FPGA
LED_RUN_FPGA
LED_ALM_FPGA
EC_nRST
LDHW[1]
LUHW[1]
SHW_CLK
SHW_FH
EC_AD[0-15]
EC_PAR
EC_nCBE1
EC_nCBE0
EC_nFRAME
EC_nPERR
EC_nSTOP
EC_nTRDY
EC_CLK
EC_nCDET
EC_nINT
CT_D[0-7]
CT_NETAEF
CT_C8
CT_FRAME
RINGER
MASTER/nS_FPGA
M/nS_FPGA
POWER_TYPE1_FPGA
POWER_TYPE0_FPGA
RS232_DCD2_CON
RS232_DSR2_CON
RS232_DTR2_CON
RS232_RXD2_CON
RS232_TXD2_CON
RS232_CTS2_CON
RS232_RTS2_CON
+15V_CON
+3.3VD_BB
+3.3VD
DG
DG
+2.5VD
TP_+2.5VD
+1.8VD
TP_+1.8VD
+1.25VD
TP_+1.25VD
+1.2VD
+1.8VD
+1.25VD
TP_+1.2VD
+1.2VD