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UltraSPARC User's Manual
ator asserts the internal reset for 19 clocks to force the chip into a safe state, and
then stops the internal clock and the PLL. The internal clock is left in the high
state. All external signals should be left in the normal reset state.
An external power-down signal (EPD) is activated by the clock generator at the
same time as the internal reset. This signal is used to shut down the UDB chips
and to put the E-Cache RAMs in standby mode. The UDB chips should follow a
similar sequence, generating an internal reset and then stopping the clock and
PLL. If desired, the external clock can be stopped after the EPD signal is asserted,
in order to allow reset processing to complete. Consult the UltraSPARC-I Data
Sheet for electrical and timing related specifications. (See the Bibliography for in-
formation about how to obtain the data sheet.)
This is a privileged instruction; an attempt to execute it while in non-privileged
mode causes a
privileged_opcode
Traps:
privileged_opcode
Note: Privileged software should save all necessary processor state (for
example, E-Cache flush) before entering power-down mode. SHUTDOWN
should be the last instruction executed before power-down.
13.3 Graphics Data Formats
Graphics instructions are optimized for short integer arithmetic, where the over-
head of converting to and from floating-point is significant. Image components
may be 8 or 16 bits; intermediate results are 16 or 32 bits.
13.3.1 8-Bit Format
Pixels consist of four unsigned 8-bit integers contained in a 32-bit word. Typical-
ly, they represent intensity values for an image (e.g. α, B, G, R). UltraSPARC sup-
ports
•
Band interleaved images, with the various color components of a point in the
image stored together, and
•
Band sequential images, with all of the values for one color component stored
together.
Sun Microelectronics
196
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