Pioneer PD-30-K Service Manual page 19

5
(M3030SFEPGP)(MAIN PCB ASSY: IC3001)
MEMORY DATA 192K/12K SINGLE CHIP MICON
• Pin Arrangement
• Block Diagram
8
Port P0 Port P1
Additional function
Timer (16 bits)
Output (Timer A) 3 line
Input (Timer B) 3line
Watch dog timer
(15 bits)
DMAC
(2 channel)
5
6
8 8 8
Port P2 Port P3
A/D converter
(10 bits x 18 channel)
UART or Clock sync
serial I/O
(3 channel)
CRC operation circuit (CCITT system)
(generation many clauses expression:
16 12 5
X + X + X + 1
M16C/60 series CPU core
R0H R0L
R1H R1L
R2
R3
A0
A1
FB
6
7
8 8
Port P4 Port P5 Port P6
System clock genarate
XIN-XOUT
XCIN-XCOUT
Memory
SB
ROM
USP
ISP
RAM
INTB
PC
FLG
multiplier
PD-30-K
7
8
8
8
A
B
C
D
E
F
19