Denon DVP-602CI Service Manual page 28

Pin Pin Name Symbol
76 P12/D10 SUBnCONFIG
77 P11/D9 DSP1 VPP
78 P10/D8 SUBDATA_O
79 P07/D7 SUBCONF_DONE
80 P06/D6
81 P05/D5 SUBnCS
82 P04/D4 SUBASDI
83 P03/D3 INT1
84 P02/D2 PLDTCK_A
85 P01/D1 PLDTDO_V
86 P00/D0 DIRRST1
87 P107/AN7 DSP2 RST
88 P106/AN6 DSP1 RST
89 P105/AN5 DSPROMRST
90 P104/AN4 DSP1 FLAG0
91 P103/AN3 DSP2 FLAG0
92 P102/AN2 DSP2 ICS
93 P101/AN1 DSP1 ICS
94 AVSS AVSS
95 P100/AN0 SUBDCLK
96 VREF VREF
97 AVCC AVCC
98 P97/SIN4 DSPMISO
99 P96/SOUT4 DSPMOSI
100 P95/CLK4 DSPICLK
Note: Pin No. : Terminal number of microcomputer.
Port Name : The name entered in the data sheet of microcomputer.
Symbol : Symbolized interface function.
I/O : Input or out of part.
"I"
"O"
Type : Composition of port in case of output port.
"C"
"N"
"P"
Op : Pull up/Pull down selection information.
"Iu"
"Id"
"Eu"
"Ed"
Det : Indicates judging state of input port. Level detection is "LV"; Edge detection is "Ed"; Detection by both shifting is "E&L";
Serial data detection is "S" (Serial data output is also "S").
Res : State at reset.
"H"
"L"
"Z"
STBY : State of port when STANDBY mode.
"O/L" = Output port and "L"
"I"
Stop : State of port when Stop mode.
"O/L" = Output port and "L"
"I"
I/O Type Det
O C -
O C -
I - Lv
I - Lv
O C -
O C -
O C -
I - E ↓ &L
O C -
I - Lv
O C -
O C -
O C -
O C -
I - Lv
I - Lv
O C -
O C -
- - -
O C -
- - -
- - -
I - Lv
O C -
O C -
= Input port
= Output port
= CMOS output
= NMOS open drain output
= PMOS open drain output
= Inner microcomputer pull up
= Inner microcomputer pull down
= External microcomputer pull up
= External microcomputer pull down
= Outputs High Level at reset
= Outputs Low Level at reset
= Becomes High impedance mode at reset
= Input port
= Input port
DVP-602CI
Op(Int.) Op(Ext.) Res
- Eu - FPGA rewrite control
- Eu - Normal : H, FLASH write for DSP : L
- Ed Z FPGA rewrite control(MAIN FPGA&GUI FPGA combined use)
- Ed Z FPGA rewrite control(MAIN FPGA&GUI FPGA combined use)
- Ed Z Not used
- Eu Z FPGA rewrite control(MAIN FPGA&GUI FPGA combined use)
- Eu Z FPGA rewrite control(MAIN FPGA&GUI FPGA combined use)
- Ed Z DIR control pin(LC89057W-VF4-E)
- - Z PLD rewrite control(JTAG), OPEN other than communication time
- - Z PLD rewrite control(JTAG)
- - Z DIR control pin(LC89057W-VF4-E)
- Ed Z DSP2(ADSP-21367)reset output pin(reset : L)
- Ed Z DSP1(ADSP-21366)reset output pin(reset : L)
- Ed Z DSP memory reset output pin(reset : L)
- Ed Z DSP1 control pin(ADSP-21366)
- Ed Z DSP2 control pin(ADSP-21367)
- Eu Z DSP2 control pin(ADSP-21367)
- Eu Z DSP1 control pin(ADSP-21366)
- - - AD GND
- - Z FPGA rewrite control
- - - AD ref. +3.3V
- - - AD +3.3V
- Eu Z DSP control pin(ADSP-21366)/(ADSP-21367)
- Eu Z DSP control pin(ADSP-21366)/(ADSP-21367)
- Eu Z DSP control pin(ADSP-21366)/(ADSP-21367)
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Function