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T X E M P T Y I N T R
Write Acknowledge Reg. with
TXEMPTY Bit Set
R e a d T X E M P T Y & T X I N T R
T X E M P T Y = 1
T X E M P T Y = 0
T X E M P T Y = X
&
&
&
T X I N T = 0
T X I N T = 0
T X I N T = 1
(Everything went through
(Waiting for Completion)
(Transmission Failed)
successfully)
Read Pkt. # Register & Save
Write Address Pointer
Register
Read Status Word from RAM
Update Statistics
Update Variables
Issue "Release" Command
Acknowledge TXINTR
Re-Enable TXENA
Restore Packet Number
Return to ISR
FIGURE 14 - TXEMPTY INTR
77
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