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SMC Networks SMC91C95 Product Manual

Isa/pcmcia full duplex single-chip ethernet and modem controller with ram
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ISA/PCMCIA Full Duplex Single-Chip
Ethernet and Modem Controller with RAM
ISA/PCMCIA Single Chip Ethernet Controller
With Modem Support
6 Kbytes Built-In RAM
Supports IEEE 802.3 (ANSI 8802-3) Ethernet
Standards
Full Duplex Support
Hardware Memory Management Unit
Built-In AUI and 10BASE-T Network
Interfaces
Simultasking
- Early Transmit and Early
Receive Functions
Advanced Power Management
Features/Including Magic Packet Frame
Control
Software Compatible with SMC91C92/
SMC91C94 (in ISA Mode)
Configuration Registers Implement Cardbus
Multi-Function Specification V3.0 with
Backward Compatibility to V2.1
Interfaces Directly to Lucent Technologies and
Rockwell International Modem Chipsets
On-Chip Attribute Memory (CIS) of up to 512
Bytes (On Even Addresses) For Card
Configuration Information; Expandable
Externally
Option for Serial or Parallel EEPROM for CIS
Simultasking is a trademark and SMC is a registered trademark of Standard Microsystems Corporation

FEATURES

Optional External Flash Capability for XIP
(Execute in Place)
Automatic Technology to Detect TX/RX
10BASE-T Tranceiver Pair Miswiring
Low Power CMOS Design
Supports Magic Packet Wakeup
128 Pin VTQFP Package
Bus Interface
Direct Interface to ISA and PCMCIA with
No Wait States
High Impedance Speaker Interface
Flexible Bus Interface
16-Bit Data and Control Paths
Fast Access Time (40 ns)
Pipelined Data Path
Handles Block Word Transfers for Any
Alignment
High Performance Chained ("Back-to-
Back") Transmit and Receive
Flat Memory Structure for Low CPU
Overhead
Dynamic Memory Allocation Between
Transmit and Receive
Buffered Architecture, Insensitive to Bus
Latencies (No Overruns/Underruns)
Supports Boot PROM for Diskless ISA
Applications
SMC91C95
PRELIMINARY

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Summary of Contents for SMC Networks SMC91C95

  • Page 1: Features

    Configuration Information; Expandable Externally Option for Serial or Parallel EEPROM for CIS Simultasking is a trademark and SMC is a registered trademark of Standard Microsystems Corporation SMC91C95 FEATURES Optional External Flash Capability for XIP (Execute in Place) Automatic Technology to Detect TX/RX...

  • Page 2: Table Of Contents

    Related Documentation PCMCIA 2.1 Standard (for PCMCIA timing and functionality) PCMCIA 3.X spec (for multi-function extensions) AT&T HSM288xCF Modem Chip Set Data Sheet - July 5, 1994 Rockwell RC224ATF and C39 Modem Chip Sets Designer’s Guide TABLE OF CONTENTS 0- 7FFE ...

  • Page 3: Pin Configuration

    Automatic Retransmission, Bad Packet Rejection, and Transmit Padding External and Internal Loopback Modes AVDD TXP/nCOLL TXN/nCRS TPETXP TEPTXDP TPETXN TPETXDN AVSS nTXLED/nTXEN nRXLED/RXCLK nLINKLED/TXD nBSELED/RXD SMC91C95 SPKRIN SPKROUT nMIS16 MRDY MINT 128 Pin VTQFP MRINGIN nMRINGOA MRINGOB nMCS nMRESET MIDLEN1 nMPWDN nMPDOUT...

  • Page 4: General Description

    The SMC91C95 is portable to different CPU and bus platforms due to its flexible bus interface, flat memory structure (no pointers), and its loosely coupled buffered architecture (not sensitive to latency).
  • Page 5 ISA bus interface functions are incorporated in the SMC91C95, as well as a 4608 byte packet RAM and serial EEPROM- based setup. The user can select or modify configuration choices.
  • Page 6 PCMCIA host, decoding for the slot nROM/nPCMCIA on the SMC91C95 is left open with a pullup for ISA mode. This pin is sampled at the end of Power On Reset. If found low, the SMC91C95 is configured for PCMCIA mode.

  • Page 7: Pin Requirements

    FUNCTION SYSTEM ADDRESS BUS SYSTEM DATA BUS SYSTEM CONTROL BUS MODEM INTERFACE SERIAL EEPROM PIN REQUIREMENTS PCMCIA A0-A15 A0-A15 nFWE nFCS nCE1 nREG D0-D15 D0-D15 RESET RESET BALE nIORD nIORD nIOWR nIOWR nMEMR IOCHRDY nWAIT nIOCS16 nIOIS16 nSBHE nCE2 INTR0...
  • Page 8 FUNCTION CRYSTAL OSC. POWER GROUND 10BASE-T INTERFACE AUI INTERFACE COLN TXP/nCOLL LEDs nRXLED/RXCLK MISC. PWRDWN/TXCLK TOTAL PINS PCMCIA XTAL1 XTAL1 XTAL2 XTAL2 AVDD AVDD AGND AGND TPERXP TPERXP TPERXN TPERXN TPETXP TPETXP TPETXN TPETXN TPETXDP TPETXDP TPETXDN TPETXDN RECP RECP RECN RECN COLP...

  • Page 9: Description Of Pin Functions

    I/O4 with This pin is sampled at the end of RESET. pullup When this pin is sampled low the SMC91C95 is configured for PCMCIA operation and all pin definitions correspond to the PCMCIA mode. For ISA operation this pin is left open...
  • Page 10 PCMCIA - Output. Optionally used by the SMC91C95 to extend host cycles. I/O24 Bidirectional. 16 bit data bus used to access the SMC91C95 internal registers. The data bus has weak internal pullups. Supports direct connection to the system bus without external buffering.
  • Page 11 Register. This interrupt is tri-stated when not selected. OD24 ISA - Active low output asserted in 16 bit mode when AEN is low and A4-A15 decode to the SMC91C95 address programmed into the high byte of the Base Address Register. The high(1)
  • Page 12 Powerdown TYPE DESCRIPTION PCMCIA - Active low output asserted whenever the SMC91C95 is in 16 bit mode, and “Enable Function” bit in the ECOR register is high, nREG is low and A4-A15 decode to the LAN address specified in I/O Base Registers 0 and 1 in PCMCIA attribute space.
  • Page 13 DESCRIPTION Powerdown output to modem controller. This pin is active (high) when either the PWRDWN bit (CSR bit 2) is set or the modem is disabled (not configured). Ring input from the modem controller. Toggles when ringing, low when not ringing.
  • Page 14 Data TYPE DESCRIPTION I with pullup Input. When low, it indicates a 16 bit modem, otherwise the modem is 8 bit wide. Used to determine if nIOIS16 (PCMCIA) and nIOCS16 (ISA) need to be asserted for modem cycles. The value of this pin may change from cycle to cycle.
  • Page 15 I with pullup Input. When low the SMC91C95 is configured for 16 bit bus operation. If left open the SMC91C95 works in 8 bit bus mode. 16 bit configuration can also be programmed via serial EEPROM (In ISA Mode only) or via software initialization of the CONFIGURATION REGISTER.
  • Page 16 TPETXN to generate the 10BASE-T transmit pre-distortion. I with pullup Internal ENDEC - Powerdown input. It keeps the SMC91C95 in powerdown mode when high (open). Must be low for normal operation. Refer to the Powerdown Matrix following for further details.

  • Page 17: Buffer Types

    Iclk Clock input buffer TYPE DESCRIPTION I with pullup When tied low the SMC91C95 is configured for external ENDEC. When tied high or left open the SMC91C95 will use its internal encoder/decoder. +5V power supply pins +5V analog power supply pins...
  • Page 18 10BASET CABLE SIDE Figure 1 - SMC91C95 System Block Diagram for ISA Bus with Boot PROM...
  • Page 19 SMC91C95 D0-D15 nIOIS16 nINPACK nWAIT nFWE nFCS EXTENDED ATTRIBUTE D0-D7 EPROM 2816 A0-X (Optional) Figure 2 - SMC91C95 System Block Diagram for Dual Function PCMCIA Card 10BASE-T/AUI SPKROUT nMRESET nRESET MINT nMCS MRDY MODEM CHIPSET PWDN MPWDN MRINGIN RINGIN...
  • Page 20 MODEM DATA INTERFACE ADDRESS MANAGEMENT INTERFACE CONTROL Figure 3 - SMC91C95 Internal Block Diagram ENDEC CSMA/CD ARBITER TWISTED PAIR TRANSCEIVER 10BASE-T...

  • Page 21: Functional Description

    FUNCTIONAL DESCRIPTION The SMC91C95 consists of an integrated Ethernet controller mapped entirely in I/O space, as well as support for an external Modem controller also mapped in I/O space. In addition, PCMCIA attribute memory space is decoded to interface an external CIS ROM, with configuration registers as per PCMCIA 3.X extensions implemented on-chip...
  • Page 22 IOis8 = ECSR register bit 5 nEN16 = pin nEN16 For the modem function, the transactions are similarxcept that the modem is assumed to be 8 bit wide unless (IOis8=0) and (nMIS16=0). NOTE: The IOis8 value should be identical in MCSR and ECSR if both functions are enabled.
  • Page 23 In the system memory space, up to 64 kbytes are after initial decoded by the SMC91C95 as expansion ROM. The ROM expansion area is 8 bits wide. Device configuration is done using a serial EEPROM, with support for modifications to the EEPROM at installation time.
  • Page 24 The SMC91C95 provides a 16-bit data path into RAM. The RAM is private and can only be accessed by the system via the arbiter.
  • Page 25 POINTER REGISTER 11-BIT LOGICAL ADDRESS RCV VS. TX AREA SELECTION FIGURE 4 - MAPPING AND PAGING VS. RECEIVE AND TX AREA TX PACKET NUMBER 2K TX AREA RX PACKET NUMBER 2K RX AREA PHYSICAL MEMORY PAGE = 256 bytes...
  • Page 26 PACKET NUMBER REGISTER PACKET #A SIDE TX FIFO PACKET #B CSMA TX COMPLETION FIFO PACKET #C FIFO PORTS REGISTER FIGURE 5 - TRANSMIT QUEUES AND MAPPING STATUS COUNT DATA STATUS COUNT DATA STATUS COUNT DATA LINEAR ADDRESS MMU MAPPING MEMORY...
  • Page 27 FIFO PORTS REGISTER PACKET #D SIDE RX FIFO PACKET #E FROM CSMA FIGURE 6 - RECEIVE QUEUE AND MAPPING STATUS COUNT DATA STATUS COUNT DATA LINEAR ADDRESS MMU MAPPING MEMORY...
  • Page 28 FIGURE 7 - SMC91C95 INTERNAL BLOCK DIAGRAM WITH DATA PATH...
  • Page 29 PACKET FORMAT IN BUFFER MEMORY The packet format in memory is similar for the TRANSMIT and RECEIVE areas. word is reserved for the status word, the next bit15 R A M O F F S E T (DECIMAL) R E S E R V E D 1536 Max C O N T R O L B Y T E FIGURE 8 - DATA PACKET FORMAT...
  • Page 30 On receive, all bytes are provided by the CSMA side. The 802.3 Frame Length word (Frame Type in Ethernet) is not interpreted by the SMC91C95. It is treated transparently as data both for transmit and receive operations. CONTROL BYTE - The CONTROL BYTE always resides on the high byte of the last word.
  • Page 31 RECEIVE FRAME STATUS WORD This word is written at the beginning of each receive frame in memory. It is not available as a register. HIGH ALGN BROD BYTE CAST BYTE ALGNERR - Frame had alignment error. BRODCAST - Receive frame was broadcast. BADCRC - Frame had CRC error.

  • Page 32: Interrupt Structure

    INTERRUPT STRUCTURE The SMC91C95 merges two main interrupt sources into a single interrupt line. One source is the Ethernet interrupt and the other is the modem interrupt. The Ethernet interrupt is conceptually equivalent to the SMC91C92 interrupt line; it is the OR function of all enabled interrupts within the Ethernet core.

  • Page 33: Reset Logic

    PCMCIA Configuration Register. POR - Internal circuit activated by Power nMRESET - Output pin to reset modem SRESET - Soft Reset bit in ECOR and MCOR, one SRESET bit for each function. SOFT RST - EPH Soft Reset bit in RCR...

  • Page 34: Powerdown Logic

    PWRDN bit in Control Register is high SMC91C95 Powerdown States: A) The SMC91C95 is Off and no Clock is running B1) The SMC91C95 of Off with clock running (No Active LAN or Host Data Transfer) TBD Current Reduction with No Link Pulses for...

  • Page 35: Pcmcia Attribute Memory: Address 0- 7Ffeh

    EEPROM device when using up to 512 bytes of “Card Information” and, if additional memory is needed, an external EEPROM may be used. When the SMC91C95 goes into powerdown POWERDOWN POWERS EXITED...

  • Page 36: Internal Vs External Attribute Memory Map

    EXTERNAL EPROM MEMORYADDRESS 0 - 7FFEh 8000h - 803Eh SMC91C95 need not be used (if serial EEPROM is being used). Internal to the SMC91C95, the memory addressing logic will allow byte or word on odd byte address access (A0=1), the SMC91C95...
  • Page 37 Regardless of the functional description, when the SMC91C95 is in 16 bit mode, all registers can be accessed as words or bytes. The default bit values upon hard reset are highlighted below each register.
  • Page 38 Table 9 - Internal I/O Space Mapping BANK0 BANK1 CONFIG BASE STATUS IA0-IA1 COUNTER IA2-IA3 IA4-IA5 GENERAL PURPOSE RESERVED CONTROL BANK BANK SELECT SELECT BANK2 BANK3 MT0-MT1 COMMAND PNR ARR MT2-MT3 FIFO PORTS MT4-MT5 POINTER MT6-MT7 DATA MGMT DATA REVISION INTERRUPT ERCV BANK...
  • Page 39 I/O location of the SMC91C95. TYPE READ/WRITE The BANK SELECT REGISTER is always accessible regardless of the value of BS0-BS2. The SMC91C95 implements only four banks in ISA mode, therefore, accesses to non-existing banks (BS2=1) are ignored. accessible in PCMCIA mode. BANK# None...
  • Page 40 HIGH FDSE BYTE PAD_E BYTE FDSE - Full Duplex Switched Ethernet. When set, the SMC91C95 is configured for Full Duplex Switched Ethernet, it defaults clear to normal CSMA/CD protocol. FDSE SMC91C95 transmit and receive processes are fully independent, namely no deferral and no collision detection are implemented.
  • Page 41 FDUPLX EPH_LOOP TXENA - Transmit enabled when set. Transmit is disabled if clear. When the bit is cleared, the SMC91C95 will complete the current transmission before stopping. When stopping due to an error, this bit is automatically cleared. LOOP LOOPS AT...
  • Page 42 I/O SPACE - BANK0 OFFSET NAME EPH STATUS REGISTER This register stores the status of the last transmitted frame. This register value, upon individual transmit packet completion, is stored as the first word in the memory area allocated to the packet. Packet interrupt processing should use the copy in memory as the register itself will be updated by subsequent packet transmissions.
  • Page 43 detection magic packet nWAKEUPEN pin (92 QFP) or WAKEUP_EN in CTR. NOTE: If the MP mode is activated using the nWAKEUPEN pin, the pin must be deasserted to exit the mode. TX_DEFR - Transmit Deferred. When set, carrier was detected during the first 6.4 sec of the inter frame gap.
  • Page 44 BYTE BYTE SOFT_RST - Software activated Reset. Active high. Initiated by writing this bit high and terminated by writing the bit low. The SMC91C95 configuration preserved, Configuration, Base, and IA0-IA5 Registers. The EEPROM in both ISA and PCMCIA mode is not reloaded after software reset.
  • Page 45 I/O SPACE - BANK0 OFFSET NAME COUNTER REGISTER Counts four parameters for MAC statistics. When any counter reaches 15 an interrupt is issued. All counters are cleared when reading the register and do not wrap around beyond 15. HIGH NUMBER OF EXC. DEFFERED TX BYTE MULTIPLE COLLISION COUNT BYTE...
  • Page 46 TYPE READ ONLY MEMORY SIZE (IN BYTES *256 * M) MEMORY SIZE - This register can be read to determine the total memory size, and will always read 18H (6144 bytes) for the SMC91C95. command. MEMORY SIZE ACTUAL MEMORY REGISTER...
  • Page 47 I/O SPACE - BANK0 OFFSET NAME MEMORY CONFIGURATION REGISTER HIGH BYTE MEMORY RESERVED FOR TRANSMIT (IN BYTES * 256 * M) BYTE MEMORY RESERVED TRANSMIT Programming this value allows the host CPU to reserve memory to be used later for transmit, limiting the amount of memory that receive packets can use up.
  • Page 48 SMC91C95 disables link test functions by not generating nor monitoring the network for link pulses. In this mode the SMC91C95 will transmit packets regardless of the link test, the EPHSR LINK_OK bit will be set and the LINK LED will stay on.
  • Page 49 INT SEL1 INT SEL0 INTERRUPT PIN USED INTR0 INTR1 INTR2 INTR3...
  • Page 50 ISA mode against the I/O address on the bus to determine the IOBASE for SMC91C95 registers. The 64k I/O space is fully decoded by the SMC91C95 down to a 16 location space, therefore the unspecified address lines A4, A10, A11 and A12 must be all zeros.
  • Page 51 IEEE Ethernet Address stored in the EEPROM. Once this data is stored in the CIS SRAM data buffer in the SMC91C95, it is parsed by the host to extract the IEEE Address information and stored manualy by the LAN Driver.
  • Page 52 This register will be used for EEPROM read and write only when the EEPROM SELECT bit in the Control Register is set. This allows generic EEPROM read and write routines that do not affect the basic setup of the SMC91C95. SYMBOL...
  • Page 53 PWRDN - Active high bit used to put the Ethernet function in powerdown mode. Cleared by: A write to any register in the SMC91C95 I/O space Hardware reset “Magic Packet” was received This bit is combined with the Pwrdwn bit in ECSR and with the powerdown bit to determine when the function is powered down.
  • Page 54 EEPROM status, will NOT have any effect on the internal registers. The CPU can resume accesses to the SMC91C95 after both bits are low. A worst case RELOAD operation initiated by RESET or by software takes less than 750 sec.
  • Page 55 Word 2 - Low Byte Word 2 - High Byte Word FE - Low Byte Word FE- High Byte Word FF - Low Byte Word FF - High Byte SMC91C95 SRAM IN BYTES Byte 0 Byte1 Byte2 Byte3 Byte FC...
  • Page 56 I/O SPACE - BANK2 OFFSET NAME MMU COMMAND REGISTER This register is used by the CPU to control the memory allocation, de-allocation, TX FIFO and RX FIFO control. The three command bits determine the command issued as described below: HIGH BYTE COMMAND BYTE...
  • Page 57 ENQUEUE PACKET NUMBER INTO TX FIFO - This is the normal method of transmitting a packet just loaded into RAM. The packet number to be enqueued is taken from the PACKET NUMBER REGISTER. RESET TX FIFOs - This command will reset both TX FIFOs: the TX FIFO holding the packet numbers awaiting transmission and the TX Completion FIFO.
  • Page 58 I/O SPACE - BANK2 OFFSET NAME PACKET NUMBER REGISTER PACKET NUMBER AT TX AREA - The value written into this register determines which packet number is accessible through the TX area. Some MMU commands use the number stored in this OFFSET NAME ALLOCATION RESULT REGISTER...
  • Page 59 I/O SPACE - BANK2 OFFSET NAME FIFO PORTS REGISTER This register provides access to the read ports of the Receive FIFO and the Transmit completion FIFO. The packet numbers to be processed by the interrupt service routines are read from this register. HIGH REMPT BYTE...
  • Page 60 I/O SPACE - BANK2 OFFSET NAME POINTER REGISTER HIGH AUTO BYTE INCR. BYTE POINTER REGISTER -The value of this register determines the address to be accessed within the transmit or receive areas. It will auto-increment on accesses to the data register when AUTO INCR. is set.
  • Page 61 This register is mapped into two uni-directional FIFOs that allow moving words to and from the SMC91C95 regardless of whether the pointer address is even or odd. Data goes through the write FIFO into memory, and is pre-fetched from memory into the read FIFO.
  • Page 62 I/O SPACE - BANK2 OFFSET NAME INTERRUPT STATUS REGISTER ERCV EPH INT OFFSET NAME INTERRUPT ACKNOWLEDGE REGISTER ERCV OFFSET NAME INTERRUPT MASK REGISTER ERCV EPH INT This register can be read and written as a word or as two individual bytes. The Interrupt Mask Register bits enable the appropriate bits when high and disable them when low.
  • Page 63 WAKE_UP - “Magic Packet” is received if enabled RX_OVRN INT - Set when the receiver overruns due to a failed memory allocation. The RX_OVRN bit of the EPHSR will also be set, but if a new packet is received it will be cleared. The RX_OVRN INT bit, however, latches the overrun condition for the purpose of being polled or generating an interrupt, and will only be cleared by...
  • Page 64 FIGURE 9 - INTERRUPT STRUCTURE...
  • Page 65 I/O SPACE - BANK 3 OFFSET NAME 0 THROUGH 7 MULTICAST TABLE BYTE HIGH BYTE BYTE HIGH BYTE BYTE HIGH BYTE BYTE HIGH BYTE The 64 bit multicast table is used for group address filtering. The hash value is defined as the six most significant bits of the CRC of the destination addresses.
  • Page 66 I/O SPACE - BANK3 OFFSET NAME MANAGEMENT INTERFACE HIGH BYTE BYTE nXNDEC - Read only bit reflecting the status of the nXENDEC pin. IOS0-IOS2 - Read only bits reflecting the status of the IOS0-IOS2 pins. MDO - The value of this bit drives the EEDO pin when MDOE=1.
  • Page 67 BYTE CHIP - Chip ID. Can be used by software drivers to identify the device used. CHIP ID VALUE TYPE READ ONLY REV - Revision ID. Incremented for each revision of a given device. DEVICE SMC91C90/SMC91C92 SMC91C94 SMC91C95 FEAST SYMBOL...
  • Page 68 I/O SPACE - BANK 3 OFFSET NAME EARLY RCV REGISTER HIGH BYTE BYTE DISCR RCV DISCRD - Set to discard a packet being received. This bit can be used in conjunction with ERCV THRESHOLD and ERCV INT to process a packet header while it is being received and sicard it if the packet is not desired.

  • Page 69: Theory Of Operation

    Headers can be analyzed without reading out the entire packet. The packet can be moved in or out with a block move operation. Multiple upper layer support - The SMC91C95 facilitates interfacing to multiple upper layer protocols because of the receive packet THEORY OF OPERATION processing flexibility.

  • Page 70: "Magic Packet" Support

    FDSE (Full Duplex Switched Ethernet). Enabled by FDSE bit in TCR bit. When the SMC91C95 is configured for FDSE, its transmit and receive paths will operate independently some functions are disabled such as Carrier Sense. Behavior in FDSE Mode The main 802.3 section affected by FDSE is 4.2.8 where the Frame Transmission procedural...
  • Page 71 TYPICAL FLOW OF EVENTS FOR TRANSMIT S/W DRIVER 1 ISSUE ALLOCATE MEMORY FOR TX - N BYTES - the MMU attempts to allocate N bytes of RAM. 2 WAIT FOR SUCCESSFUL COMPLETION CODE - Poll until the ALLOC INT bit is set or enable its mask bit and wait for the interrupt.
  • Page 72 TYPICAL FLOW OF EVENTS FOR RECEIVE S/W DRIVER 1 ENABLE RECEPTION - By setting the RXEN bit. 5 SERVICE INTERRUPT - Read the Interrupt Status Register and determine if RCV INT is set. The next receive packet is at receive area. (Its packet number can be read from the FIFO Ports Register).
  • Page 73 Save Bank Select & Address Ptr Registers Mask 91C94 Interrupts Read Interrupt Register Y es TX INTR? Call TX INTR or TXEMPTY INTR Get Next TX ALLOC INTR? Packet Available for Transmission? Y es Call ALLOCATE EPH INTR? Y es Restore Address Pointer &...
  • Page 74 FIGURE 11 - INTERRUPT GENERATION FOR TRANSMIT, RECEIVE, MMU...
  • Page 75 RX INTR Write Ad. Ptr. Reg. & Read Word 0 from RAM Destination Multicast? Read Words 2, 3, 4 from RAM for Address Filtering Address Filtering Pass? Status Word Do Receive Lookahead Get Copy Specs from Upper Layer Okay to Copy? Copy Data Per Upper Layer Specs...
  • Page 76 T X I N T R S a v e P k t N u m b e r R e g i s t e r R e a d T X D O N E P k t # f r o m F I F O P o r t s R e g .
  • Page 77 T X E M P T Y I N T R Write Acknowledge Reg. with TXEMPTY Bit Set R e a d T X E M P T Y & T X I N T R T X E M P T Y = 1 T X E M P T Y = 0 T X E M P T Y = X &...
  • Page 78 DRIVER SEND Choose Bank Select Register 2 Call ALLOCATE Exit Driver Send Read Allocation Result Register Write Allocated Packet into Packet # Register Write Address Pointer Register Copy Part of TX Data Packet into RAM Write Source Address into Proper Location Copy Remaining TX Data Packet into RAM Enqueue Packet...
  • Page 79 Note that with the memory management built into the SMC91C95, the CPU can dynamically program this parameter. For instance, when driver does...

  • Page 80: Internal Vs. External Attribute Memory Map

    512 bytes of CIS or less is required, the nFCS and nFWE output pins of the SMC91C95 need not be used (if serial EEPROM is being used). Internal to the SMC91C95, the memory addressing logic will allow byte or word access on even byte boundaries.
  • Page 81 Table 11 - Attribute Memory Decodes Using Serial EPROM ATTRIBUTE EXTERNAL EPROM MEMORYADDRESS 0 - 3FEh 400h-7FFEh 8000h - 803Eh Table 12 - Attribute Memory Decodes without Serial EPROM ATTRIBUTE EXTERNAL EPROM MEMORYADDRESS 0 - 7FFEh 8000h - 803Eh INTERNAL SRAM STORE STORE (512 BYTES) INTERNAL SRAM...

  • Page 82: Pcmcia Configuration Registers Description

    PCMCIA CONFIGURATION REGISTERS DESCRIPTION Ethernet Function (Base Address 8000h) 8000h - Ethernet Configuration Option Register (ECOR) SRESET LevIREQ BIT 7 - SRESET: This bit when set will clear all internal registers associated with the Ethernet function except itself. BIT 6 - LevIREQ: This bit is read only and reads as a one to indicate level mode interrupts are used.
  • Page 83 BIT 4 - Not defined BIT 3 - Not defined BIT 2 - PwrDwn: When set (1), this bit puts the SMC91C95 Ethernet function into powerdown mode. The Ethernet function is also put into powerdown mode when the Enable Function bit (ECOR bit 0) is cleared.
  • Page 84 I/O Base Register 0 & 1 (I/O Base 0 & 1) Address 800Ah & 800Ch 800Ah - Ethernet I/O BASE Register 0 800Ch - Ethernet I/O BASE Register 1 The I/O Base registers determine the base address of the I/O range used to access function specific registers.
  • Page 85 PCMCIA functionality, this bit must be set. BIT 0 - Enable Function: This bit enables (1) or disables (0) the Modem function. While the Modem is disabled the SMC91C95 inhibits nMCS, IREQ is not generated for the Modem function and nINPACK is not returned for accesses to the Modem registers.
  • Page 86 8022h - Modem Configuration and Status Register (MCSR) Address 8022h Changed SigChg IOIs8 Bit 7 - Changed: This bit is the logical OR of the CREADY/-Bsy and (RINGEVENT bit logically anded with RINGENABLE) states. Bit 6 - SigChg: If this bit is a one, the function is enabled (configured), the Changed bit controls the nSTSCHG pin.
  • Page 87 Rready/-Bsy bit changes state from zero(0) to one(1) or one(1) to zero(0) with the source of the change of state is a change in the modem ready (MRDY) signal. The Cready/-Bsy bit can be written by the CPU also. The CPU attempt...
  • Page 88 RINGEVENT: This bit is latched to a one at the start of each ring frequency cycle (input from ring input from modem, the MRINGIN signal going high). When this bit and RINGENABLE are both set to a one (1), the Changed bit in the MCSR is set to a one(1).
  • Page 89 I/O space. I/O Base 0 contains the low order byte (A7-A0) and I/O Base 1 contains the high order byte (A15-A8). Since the modem function requires 8 I/O locations, bits 2-0 of I/O Base 0 are always 0. Since only A15 to A4 are...
  • Page 90 ISA mode only). The Ethernet I/O space can be configured as an 8 or 16 bit space, and is similar to the SMC91C95, SMC91C92, etc. I/O space. To limit the I/O space requirements to 16 locations, the registers are split into six banks.

  • Page 91: Functional Description Of The Blocks

    FUNCTIONAL DESCRIPTION OF THE BLOCKS MEMORY MANAGEMENT UNIT The MMU interfaces the on-chip RAM on one side and the arbiter on the other for address and data flow purposes. For allocation and de- allocation, it interfaces the arbiter only. The MMU deals with a single ported memory and is not aware of the fact that there are two entities requesting...
  • Page 92 The bus interface handles the data, address and control interfaces as a superset of the ISA and PCMCIA specifications and allows 8 or 16 bit adapters to be designed with the SMC91C95 with no glue to interface to the ISA or PCMCIA bus.
  • Page 93 16 bit transfer will be at least 2 clocks for the I/O access to the SMC91C95 + one clock for the memory cycle) = 3 clocks. In absolute time it means 375ns for a 8MHz bus, and 240ns for a 12.5 MHz bus.
  • Page 94 The width of each FIFO is 5 bits per packet number. The depth of each FIFO equals the number of packets the SMC91C95 can handle (18). The guideline is software transparency; the software driver should not be aware of different devices or FIFO depths.
  • Page 95 FIGURE 16 - MMU PACKET NUMBER FLOW AND RELEVANT REGISTERS...
  • Page 96 SMC91C95, or if it is a multicast address and ALMUL bit is set, or if it is a multicast address matching one of the multicast table entries. If the PRMS bit is set, all packets are received.
  • Page 97 3. Link_count: 2 4. Link_test_max_timer: 64 ms The state of the link is reflected in the EPHSR. The SMC91C95 also provides a standard 6 wire AUI interface to a coax transceiver. PHYSICAL INTERFACE The internal physical interface (PHY) consists of an encoder/decoder (ENDEC) and an internal 10BASE-T transceiver.
  • Page 98 can be divided into transmit and receive functions. Transmit Functions Manchester Encoding The PHY encodes the transmit data received from the MAC. The encoded data is directed internally to the selected output driver for transmission over the twisted-pair network or the AUI cable.
  • Page 99 Reverse Polarity Function In the 10BASE-T mode, the PHY monitors for receiver polarity reversal due to crossed wires and corrects by reversing the signal internally. Collision Detection Function In the 10BASE-T mode, while in half duplex, a collision state is indicated when there are simultaneous transmissions and receptions on the twisted pair link.

  • Page 100: Board Setup Information

    In order to support a software utility based installation, even if the EEPROM was never programmed, the EEPROM can be written using the SMC91C95. One of the IOS combination is associated with a fixed default value for the key parameters (I/O BASE, ROM...
  • Page 101 STORE and RELOAD bits of CTR will readback as both bits high. No other bits of the SMC91C95 can be read or written until the EEPROM operation completes and both bits are clear. This mechanism is also valid for reset initiated reloads.
  • Page 102 For example, if an odd pointer value is loaded, first a byte is pre-fetched into the FIFO, and immediately full word completing three bytes into the FIFO. If the CPU reads a word, one byte will be left again a new word is pre-fetched.
  • Page 103 IOS2-0 WORD ADDRESS FIGURE 17 - 64 X 16 SERIAL EEPROM MAP FOR ISA MODE 16 BITS CONFIGURATION REG. BASE REG. CONFIGURATION REG. BASE REG. CONFIGURATION REG. BASE REG. CONFIGURATION REG. BASE REG. CONFIGURATION REG. BASE REG. CONFIGURATION REG. BASE REG. CONFIGURATION REG.

  • Page 104: Operational Description

    OPERATIONAL DESCRIPTION MAXIMUM GUARANTEED RATINGS* Operating Temperature Range ... 0 Storage Temperature Range ...-55 Lead Temperature Range (soldering, 10 seconds) ... +325 Positive Voltage on any pin, with respect to Ground ...Vcc + 0.3V Negative Voltage on any pin, with respect to Ground ... -0.3V Maximum Vcc ...
  • Page 105 PARAMETER SYMBO Input Leakage (All I and IS buffers except pins with pullups/pulldowns) Low Input Leakage High Input Leakage IP Type Buffers Input Current ID Type Buffers Input Current I/04 Type Buffer Low Output Level High Output Level Output Leakage I/024 Type Buffer Low Output Level High Output Level...
  • Page 106 PARAMETER SYMBO OD16 Type Buffer Low Output Level Output Leakage OD162 Type Buffer Low Output Level High Output Level Output Leakage OD24 Type Buffer Low Output Level Output Leakage Supply Current Active Supply Current Standby CSBY CAPACITANCE T = 25 C;...
  • Page 107 PARAMETER Receiver Threshold Voltage Receiver Squelch Receiver Common Mode Range Transmitter Output: Voltage Source Resistance Transmitter Output DC Offset Transmitter Backswing Voltage to Idle Differential Input Voltage Receiver Threshold Voltage Receiver Squelch Receiver Common Mode Range Transmitter Output Voltage (R=78 ) Transmitter Backswing Voltage to Idle Input Differential Voltage Output Short Circuit (to V...

  • Page 108: Timing Diagrams

    Access Time nOE Access Time Output Disable Time from nCE1 high Output disable Time from nOE high NOTE: Applies only when nWAIT is asserted by the SMC91C95. FIGURE 18 - PCMCIA MEMORY READ TIMING TIMING DIAGRAMS 5 max DATA VALID Parameter...
  • Page 109 Data Hold Time from nWE High Write Recovery Time (Address, nREG Hold from nWE High) NOTE: Minimum write pulse width must be met whether or not nWAIT is asserted by the SMC91C95 FIGURE 19 - PCMCIA MEMORY WRITE TIMING 250 min Parameter...
  • Page 110 A[15:0] nMCS nREG nIORD nINPACK nIOIS16 D[15::0] FIGURE 20 - I/O READ TIMING (Table on the following page)
  • Page 111 Parameter Address setup before nIORD low nCEI, nCE2 setup before nIORD low nREG setup before nIORD low nIORD low width Address hold from nIORD high nCE1, nCE2 hold following nIORD high nREG hold following nIORD high Address valid to nINPACK low nCE1, nCE2 low to nINPACK low nREG low to nINPACK low nIORD low to nINPACK low...
  • Page 112 A[15:0] nMCS nREG nCE1 nCE2 nIOWR nIOIS16 D[15::0] FIGURE 21 - (I/O WRITE TIMING) (Table on the following page)
  • Page 113 Parameter Address setup before nIOWR low nCE1, nCE2 setup before nIOWR low nREG setup before nIOWR low nIOWR low width Address hold from nIOWR high nCE1, nCE2, hold following nIOWR high nREG hold following nIOWR high Address valid to nIOIS16 valid Data hold following nIOWR Address valid to nMCS low nCE1 low to nMCS low...
  • Page 114 A0-9,A15 valid nREG nCE1 D0-7 valid Parameter Write Data Setup to nWE Rising Write Data Hold after nWE Rising nOE Low to Valid Data Address, nREG Setup to nWE Active Address, nREG Hold after nOE Inactive Address, nREG Setup to nOE Active Address, nREG Hold after Control Inactive nCE1 Setup to nWE Rising nCE1 Low to Valid Data...
  • Page 115 A0-9,A15 valid nREG nCE1,nCE nIORD D0-15 nINPAC Parameter nIORD Delay to nREG Low to Control nCE1,nCE2 Setup to Control Cycle Time (No Wait nREG Hold after Control nCE1,nCE2 Hold after Control Address Setup to Control Address Hold after Control nIORD Active to Data FIGURE 23 - PCMCIA CONSECUTIVE READ CYCLES valid units...
  • Page 116 A0-9,A15 valid nREG nCE1,nCE2 nIOWR valid D0-15 Parameter nREG Low Setup to Control Active nCE1,nCE2 Setup to Control Active nREG Hold after Control Inactive nCE1,nCE2 Hold after Control Inactive Address Setup to Control Active Address Hold after Control Inactive Cycle Time (No Wait States) Write Data Setup to nIOWR Rising Write Data Hold after nIOWR Rising FIGURE 24 - CONSECUTIVE PCMCIA WRITE CYCLES...
  • Page 117 A0-9,A15 valid nREG nCE1 nFCS nFWE Parameter nWE to nFWE Delay Address, nREG, nCE1 Delay to nFCS FIGURE 25 - PCMCIA ATTRIBUTE MEMORY READ/WRITE (A15=0) valid units...
  • Page 118 nMPWDN] MRINGOUTB Parameter MRINGOUTB Pulse Entering Powerdown MRINGOUTB Pulse Exiting Powerdown FIGURE 26 - RINGOUT FOR L39/C39 ROCKWELL MODEMS ENTERING/EXITING POWERDOWN Units...
  • Page 119 A0-15 AEN, nSBHE VALID ADDRESS nIOCS16 nIORD D0-15 Parameter Address, nSBHE, AEN Setup to Control Active Address, nSBHE, AEN Hold after Control Inactive nIORD Low to Valid Data nIORD High to Data Floating A4-A15, AEN Low, BALE High to nIOCS16 Cycle time* BALE Tied High IOCHRDY not used - t20 has to be met...
  • Page 120 A0-15 AEN, nSBHE VALID ADDRESS nIOCS16 nIOWR VALID DATA IN D0-15 Parameter Address, nSBHE, AEN Setup to Control Active Address, nSBHE, AEN Hold after Control Inactive Data Setup to nIOWR Rising Data Hold after nIOWR Rising A4-A15, AEN Low, BALE High to nIOCS16 Cycle time* BALE Tied High IOCHRDY not used - t20 has to be met...
  • Page 121 A0-15 AEN, VALID ADDRESS nSBHE nIOCS16 nIORD nIOWR IOCHRDY D0-D15 Parameter Control Active to IOCHRDY Low IOCHRDY Low Pulse Width* Cycle time** *Note: Assuming NO WAIT ST = 0 in configuration register and cycle time observed. **Note: The cycle time is defined only for accesses to the Data Register as follows: For Data Register Read - From nIORD falling to next nIORD falling For Data Register Write - From nIOWR rising to next nIOWR rising FIGURE 29 - ISA CONSECUTIVE READ AND WRITE CYCLES...
  • Page 122 A0-15 (ISA) AEN, nSBHE nIOCS16 nIORD IOCHRDY D0-D15 Parameter Control Active to IOCHRDY Low IOCHRDY Width when Data is Unavailable at Data Register Valid Data to IOCHRDY Inactive IOCHRDY is used instead of meeting t20 and t43. "No Wait St' bit is 1 - IOCHRDY only negated if needed and only for Data Register access. FIGURE 30 - DATA REGISTER SPECIAL READ ACCESS VALID ADDRESS VALID DATA...
  • Page 123 A0-15 (ISA) AEN, nSBHE nIOCS16 nIOWR IOCHRDY D0-D15 Parameter Control Active to IOCHRDY Low IOCHRDY Width when Data Register is Full IOCHRDY is used instead of meeting t20 and t44. 'No Wait St' bit is 1 - IOCHRDY only negated if needed and only for Data Register access. FIGURE 31 - DATA REGISTER SPECIAL WRITE ACCESS VALID ADDRESS VALID DATA IN...
  • Page 124 A0-15 VALID ADDRESS (ISA) nIOWR nIORD VALID DATA OUT D0-7 Parameter Address, nSBHE, AEN Setup to Control Active nIORD Low to Valid Data Data Setup to nIOWR Rising Data Hold after nIOWR Rising FIGURE 32 - 8-BIT MODE REGISTER CYCLES A0-19 ADDRESS VALID nMEMRD...
  • Page 125 A0-15, VALID nSBHE BALE nIOCS16 nIORD nIOWR Parameter Address, nSBHE Setup to BALE Falling Address, nSBHE Hold after BALE Falling Address, nSBHE, AEN Setup to Control Active AEN Hold after Control Inactive A4-A15, AEN Low, BALE High to nIOCS16 Low t4 not needed.
  • Page 126 A0-19 VALID BALE nMEMRD nROM Parameter Address Setup to BALE Falling Address Hold after BALE Falling Address Setup to Control Active nMEMRD Low to nROM Low nMEMRD High to nROM High FIGURE 35 - EXTERNAL ROM READ ACCESS USING BALE units...
  • Page 127 EESK EEDO EEDI EECS Parameter units EESK Falling to EEDO, EECS Changing 9346 is typically the serial EEPROM used. FIGURE 36 - EEPROM READ...
  • Page 128 EESK EEDO EEDI EECS Parameter units EESK Falling to EEDO, EECS Changing 9346 is typically the serial EEPROM used. FIGURE 37 - EEPROM WRITE...
  • Page 129 POINTER ADDRESS REGISTER nIOWR nIORD IOCHRDY/ nWAIT (Z) Parameter Pointer Register Reloaded to a Word of Data Prefetched into Data Register Note: If t44 is not met, IOCHRDY will be negated for the required time. This parameter can be ignored if IOCHRDY is connected to the system.
  • Page 130 nTXEN TXCLK Parameter TXD, nTXEN Delay from TXCLK Falling FIGURE 40 - EXTERNAL ENDEC INTERFACE - START OF TRANSMIT RXCLK nCRS Parameter nCRS, RXD Setup to RXCLK Falling nCRS, RXD Hold after RXCLK Falling FIGURE 41 - EXTERNAL ENDEC INTERFACE - RECEIVE DATA (RXD SAMPLED BY FALLING RXCLK) units units...
  • Page 131 TPETXP TPETXN TPETXDN TPETXDP Parameter TPETXP to TPETXN Skew TPETXP(N) to TPETXDP(N) Delay TPETXDN to TPETXDP Skew TXP to TXN Skew FIGURE 42 - DIFFERENTIAL OUTPUT SIGNAL TIMING (10BASE-T AND AUI) TWISTED PAIR DRIVERS AUI DRIVERS -1.5 units...
  • Page 132 RECP RECN nCRS (internal) TPERXP(N) nCRS (internal) Parameter Noise Pulse Width Reject (AUI) Carrier Sense Turn On Delay (AUI) Noise Sense Pulse Width Reject (10BASE-T) Carrier Sense Turn On Delay (10BASE-T) FIGURE 43 - RECEIVE TIMING - START OF FRAME (AUI AND 10BASE-T) first bit decoded first bit decoded units...
  • Page 133 last bit TPERXP TPERXN RECP RECN nCRS (internal) Parameter Receiver Turn Off Delay FIGURE 44 - RECEIVE TIMING - END OF FRAME (AUI AND 10BASE-T) units...
  • Page 134 TPETXP TPETXN Parameter Transmit Output High to Idle in Half-Step Mode Transmit Output High before Idle in Half-Step Mode FIGURE 45 - TRANSMIT TIMING - END OF FRAME (AUI AND 10BASE-T) last bit units...
  • Page 135 COLLP COLLN (internal) Parameter Collision Turn On Delay Collision Turn Off Delay FIGURE 46 - COLLISION TIMING (AUI) units...
  • Page 136 M I L L I M E T E R S Y M B O L MIN. N O M . M A X . 0.05 0.10 0.15 0.95 1.00 1.05 0.13 0.18 0.23 0.09 0.20 13.90 14.00 14.10 13.90 14.00 14.10 0.40...
  • Page 138 SMC or others. SMC reserves the right to make changes at any time in order to improve design and supply the best product possible. SMC91C95 Rev. 08/08/96...

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