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CompuLab CM-T43 Reference Manual

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  • Page 1 CM-T43 Reference Guide...
  • Page 2 To the extent permitted by law no liability (including liability to any person by reason of negligence) will be accepted by Compulab Ltd., its subsidiaries or employees for any direct or indirect loss or damage caused by omissions from or inaccuracies in this document.

  • Page 3: Table Of Contents

    Table of Contents Table of Contents INTRODUCTION ......................6 About This Document ....................6 CM-T43 Part Number Legend ..................6 Related Documents ...................... 6 OVERVIEW ........................7 Highlights ........................7 Block Diagram ......................8 CM-T43 Features ......................9 CORE SYSTEM COMPONENTS ................11 Sitara AM437x SoC ....................
  • Page 4 Operating Temperature Ranges ................. 78 APPLICATION NOTES ..................... 79 Carrier Board Design Guidelines ................79 Carrier Board Troubleshooting .................. 79 Ethernet Magnetics Implementation ................80 8.3.1 Magnetics Selection ..................80 8.3.2 Magnetics Connection ..................80 Revised September 2017 CM-T43 Reference Guide...
  • Page 5 Added notes and revised signals tables for all signals on the following CM-T43 pins (across the whole document): 4, 16, 30, 32, 34, 36, 38, 39, 40, 41, 42, 43, 44, 47, 48, 50, 51, 57, 59, 100, 102, 104, 106, 108, 110, 112, 116, 117, 118, 120, 122, 124, 126, 128, 130, 133, 134, 136, 138, 140, 149, 151, 153, 155, 161, 163, 192, 202.

  • Page 6: Introduction

    This document is part of a set of reference documents providing information necessary to operate and program CompuLab CM-T43 Computer-on-Module. CM-T43 Part Number Legend Please refer to the CompuLab website ‘Ordering information’ section to decode the CM-T43 part number: http://www.compulab.co.il/products/computer-on-modules/cm-t43/#ordering. Related Documents...

  • Page 7: Overview

    ADC × 16, CAN bus × 2, Onboard WiFi IEEE 802.11a/b/g/n/ac, Onboard Bluetooth 4.0 (supports Low Energy), Onboard NFC.  Miniature size: 36 × 68 x 5 mm  SB-SOM-T43 carrier board turns the CM-T43 system on module (CoM/SoM) into SBC- T43, a single board computer Revised September 2017 CM-T43 Reference Guide...

  • Page 8: Block Diagram

    Overview Block Diagram Figure 1 CM-T43 Block Diagram up to 1x Remote Frame Buffer 2 Ethernet Ports up to 1x Parallel Display (24bit max) (1Gbps) Cortex-A9 up to 2x Camera (VPFE) 2 x VPFE up-to 6x UART up-to 2x I2C Bus...

  • Page 9: Cm-T43 Features

    1-Wire 1-Wire interface Up to 133 multifunction signals. Can be used as GPIO (shared with other GPIO functions) Up to 16 general-purpose ADC channels System Logic Real time clock, powered by external lithium battery Revised September 2017 CM-T43 Reference Guide...
  • Page 10 Industrial: -40° to 85° C. Click for availability note Storage temperature -40° to 85° C Relative humidity 10% to 90% (operation) 05% to 95% (storage) Shock 50G / 20 ms Vibration 20G / 0 - 600 Hz Revised September 2017 CM-T43 Reference Guide...

  • Page 11: Core System Components

    EtherCAT®, PROFIBUS®, EnDat and others. Cryptographic acceleration is also available in every CM-T43 device. Secure boot can also be made available for anti-cloning and illegal software update protection.

  • Page 12: Pru-Icss

    One UART Port with Flow Control Pins, Supports Up to 12 Mbps  One Enhanced Capture (eCAP) Module  Two MII Ethernet Ports that Support Industrial Ethernet, such as EtherCAT  One MDIO Port  Industrial Communication is Supported by Two PRU-ICSS Subsystems Revised September 2017 CM-T43 Reference Guide...

  • Page 13: Multimedia System

    3.4.1 DRAM CM-T43 is equipped with up to 1GB of onboard DDR3 memory. The DDR3 data bus is 32-bits wide and operates at 400 MHz clock frequency (DDR3-800). NOTE: CM-T43 boards with 128MB of DRAM (D128 option) feature a 16-bit wide DDR3 data bus.

  • Page 14: Peripheral Interfaces

     All of the CM-T43 digital interfaces operate at 3.3V voltage levels, unless otherwise noted. The signals for each interface are described in the “Signal description” table for the interface in question. The following notes provide information on the “Signal description” tables: ...
  • Page 15 Peripheral Interfaces  "PU33" – Always pulled up to 3.3V on-board CM-T43, (typ. 5KΩ-15KΩ).  "PUSUPPLY" – Always pulled up to 3.3V - 5.0V on-board CM-T43, (typ. 5KΩ-15KΩ).  "PD" - Always pulled down on-board CM-T43, (typ. 5KΩ-15KΩ). Revised September 2017...

  • Page 16: Display Interface

    Peripheral Interfaces Display Interface CM-T43 Display interface is derived from the Sitara AM437x display subsystem (DSS). The DSS can operate in one of the following modes (depending on software configuration)  RFBI mode (implements MIPI-DBI 2.0 protocol) and supports the following features: ...
  • Page 17 161* Horizontal Sync 1 "N16G" Without "N32G" Pixel Data Bus / RFBI Data DSS_DATA2 110*^ IO; PD Always 10KΩ Pull Down onboard CM-T43 DSS_DATA20 146* Pixel Data Bus / RFBI Chip Select 0 Always Without "N4G" Without DSS_DATA20 149* Pixel Data Bus "N16G"...

  • Page 18: Camera Interfaces (Vpfe)

    / reset. Camera Interfaces (VPFE) CM-T43 camera interfaces are derived from the Sitara AM437x integrated Video Port Front End (VPFE) modules. CM-T43 includes two instantiations of the VPFE for connection to CCD cameras or BT.656 compliant video encoders. The following main features are supported: ...

  • Page 19: Local Bus (Gpmc)

     Programmable auto-clock gating support NOTE: Some of the GPMC signals are shared with onboard SLC NAND flash when CM-T43 configuration includes the “N128” or “N512” options. For additional details on GPMC, please refer to the Sitara AM437x technical reference manual. The...
  • Page 20 GPMC Address "E2" Without GPMC_A3 GPMC Address "E2" GPMC_A3 GPMC Address Always GPMC Address; Pulled high/low on SoM GPMC_A3 112*^ when normal/alternate boot sequence is Always PU33/PD selected respectively Without GPMC_A4 GPMC Address "E2" Revised September 2017 CM-T43 Reference Guide...
  • Page 21 "N32G" Without "N4G" Without GPMC_AD15 131* GPMC Address and Data "N16G" Without "N32G" Always GPMC_AD2 GPMC Address and Data (shared) Always GPMC_AD3 GPMC Address and Data (shared) Always GPMC_AD4 GPMC Address and Data (shared) Revised September 2017 CM-T43 Reference Guide...
  • Page 22 GPMC_DIR GPMC Data Direction Always GPMC Output Always GPMC_OEN_REN Read Enable (shared) GPMC_WAIT0 202* GPMC Wait 0 Always Always GPMC_WAIT0 GPMC Wait 0 (shared) GPMC_WAIT1 GPMC Wait 1 Always GPMC_WEN GPMC Write Enable Always Revised September 2017 CM-T43 Reference Guide...

  • Page 23: Analog Audio

    NOTE: Pins denoted with "^" must not be pulled or driven by carrier board during SoM power-up / reset. Analog Audio The CM-T43 analog audio functionality is implemented by interfacing the Wolfson WM8731L audio codec with the Sitara AM437x McASP0 interface. The codec supports the following features: ...

  • Page 24: Digital Audio (Mcasp)

    With "A" Digital Audio (McASP) The multichannel digital audio interface available with CM-T43 is based on the multichannel audio serial port IP integrated into Sitara AM437x SoC. Two instances of the McASP block are available with CM-T43. McASP supports the following main features: ...
  • Page 25 McASP1 Transmit Bit Clock Always MCASP1_AHCLKR McASP1 Receive Master Clock Without "E1" MCASP1_AHCLKX McASP1 Transmit Master Clock Without "E1" MCASP1_AHCLKX 139* McASP1 Transmit Master Clock Without "WB" MCASP1_AXR0 McASP1 Serial Data (IN/OUT) Without "E1" Revised September 2017 CM-T43 Reference Guide...

  • Page 26: Wlan, Bluetooth And Nfc

    / reset. WLAN, Bluetooth and NFC CM-T43 features IEEE 802.11ac/a/b/g/n 2X2 MIMO WLAN, Bluetooth & NFC. The functionality is implemented by interfacing the AzureWave AW-CH397 combo controller module with the Sitara AM437x MMC/SD/SDIO 2 interface. Based on Marvell 88W8897 chipset, the AW-CH397 supports the following features: WLAN IEEE 802.11a/b/g/n/ac, Data Rates:...

  • Page 27: Ethernet

    NOTE: The WLAN, Bluetooth and NFC module is available only with the ‘WB’ configuration option. Ethernet CM-T43 incorporates two full-featured 10/100/1000 ethernet ports implemented with the Sitara AM437x integrated MAC and the built in 3-port switch coupled with two AR8033 RGMII Ethernet PHYs from Atheros. Both ethernet interfaces support the following main features: ...

  • Page 28: Usb2.0

    NOTE: Pins denoted with "^" must not be pulled or driven by carrier board during SoM power-up / reset. USB2.0 CM-T43 is equipped with two independent USB2.0 compliant ports, implemented with two instances of the Synopsys DWC3 subsystem integrated in the Sitara AM437x SoC. The following main features are supported: ...

  • Page 29: Mmc / Sd / Sdio

    Always MMC / SD / SDIO Up to three full featured MMC/SD/SDIO ports are available with CM-T43. The ports are implemented with three instances of the MMCSD host controller integrated into the Sitara AM437x SoC. The following general features are supported: ...
  • Page 30 MMC/SD/SDIO Data Bus Always Without "N4G" MMC1_DAT3 149* MMC/SD/SDIO Data Bus Without "N16G" Without "N32G" Without "N128" MMC1_DAT4 MMC/SD/SDIO Data Bus Without "N512" Without "N4G" MMC1_DAT4 161* MMC/SD/SDIO Data Bus Without "N16G" Without "N32G" Revised September 2017 CM-T43 Reference Guide...
  • Page 31 Without "N32G" MMC2_DAT6 MMC/SD/SDIO Data Bus Without "E2" Without "N4G" MMC2_DAT6 151* MMC/SD/SDIO Data Bus Without "N16G" Without "N32G" MMC2_DAT7 MMC/SD/SDIO Data Bus Without "E2" Without "N4G" MMC2_DAT7 149* MMC/SD/SDIO Data Bus Without "N16G" Revised September 2017 CM-T43 Reference Guide...

  • Page 32: Uart

    NOTE: Pins denoted with "*" are multifunctional. For additional details please refer to chapter of this document 4.10 UART Up-to 6 UART ports are available with CM-T43. The functionality is derived from the UART modules integrated into the Sitara AM437x SoC. The following general features are supported:  16C750 compatibility ...
  • Page 33 UART Clear to Send Always UART5_CTSN 137* UART Clear to Send Without "WB" UART5_CTSN 138*^ I; PD UART Clear to Send Always UART5_RTSN UART Request to Send Always UART5_RTSN 140*^ O; PU33 UART Request to Send Always Revised September 2017 CM-T43 Reference Guide...

  • Page 34: I 2 C

    NOTE: Pins denoted with "^" must not be pulled or driven by carrier board during SoM power-up / reset. 4.11 CM-T43 is equipped with two I2C bus interfaces. The following general features are supported by both I2C bus interfaces: ...

  • Page 35: Spi

    Peripheral Interfaces 4.12 Up-to four SPI interfaces are accessible through the CM-T43 carrier board interface. The SPI interfaces are derived from Sitara AM437x integrated multichannel serial port interface (McSPI). Each instance of McSPI port can operate as either a master or as an SPI slave. The following features are supported: ...

  • Page 36: Quad Spi (Qspi)

    / reset. 4.13 Quad SPI (QSPI) CM-T43 is equipped with a Quad SPI interface. The interface is implemented with the Sitara AM437x integrated QSPI controller. The following features are supported by the QSPI controller:  Programmable divider for serial data clock generation...

  • Page 37: Can Bus

    4.14 CAN Bus CM-T43 is equipped with two instances of the CAN bus controller. Each interface is implemented with a Sitara AM437x integrated DCAN module. The following features are supported by the DCAN module:  Supports CAN protocol version 2.0 part A, B (ISO 11898-1) ...

  • Page 38: Adc And Resistive Touch-Screen

    4.15 ADC and Resistive Touch-Screen CM-T43 is equipped with two instances of the general purpose ADC controller. Each instance is implemented with a Sitara AM437x integrated ADC module. While ADC1 module can only operate as a general purpose analog to digital converter with 8 input ports, ADC0 can also operate as a resistive touch-screen controller, supporting 4-wire,5-wire and 8 wire touch panels.

  • Page 39: Hdq / 1-Wire

    4.17 GPIO Up-to 133 SoC native GPIO signals are available through the carrier board interface of CM-T43. All native GPIO signals are derived from the Sitara AM437x on-SoC GPIO modules. The GPIO pins can be configured for the following applications: ...
  • Page 40 Always GPIO0_7 General purpose input/output Always Without GPIO0_8 General purpose input/output "E1" GPIO0_8 134*^ IO; PD General purpose input/output Always Without GPIO0_9 General purpose input/output "E1" GPIO0_9 136*^ IO; PD General purpose input/output Always Revised September 2017 CM-T43 Reference Guide...
  • Page 41 General purpose input/output "E2" Without GPIO1_26 General purpose input/output "E2" Without GPIO1_27 General purpose input/output "E2" GPIO1_28 General purpose input/output Always Without "N128" GPIO1_29 162* General purpose input/output Without "N512" Without GPIO1_3 General purpose input/output "N128" Revised September 2017 CM-T43 Reference Guide...
  • Page 42 IO; PU33 General purpose input/output Always GPIO2_26 General purpose input/output Always GPIO2_27 General purpose input/output Always GPIO2_28 General purpose input/output Always GPIO2_29 General purpose input/output Always Without "N128" GPIO2_3 General purpose input/output Without "N512" Revised September 2017 CM-T43 Reference Guide...
  • Page 43 General purpose input/output Always Without GPIO4_16 General purpose input/output "WB" Without GPIO4_17 General purpose input/output "WB" Without GPIO4_18 General purpose input/output "WB" Without GPIO4_19 General purpose input/output "WB" GPIO4_2 148* General purpose input/output Always Revised September 2017 CM-T43 Reference Guide...
  • Page 44 General purpose input/output Always GPIO5_5 General purpose input/output Always GPIO5_6 General purpose input/output Always GPIO5_7 General purpose input/output Always NOTE: Pins denoted with "*" are multifunctional. For additional details please refer to chapter of this document Revised September 2017 CM-T43 Reference Guide...

  • Page 45: Enhanced Capture Module (Ecap)

    / reset. 4.18 Enhanced Capture module (eCAP) Three enhanced capture (eCAP) module instances are accessible through the CM-T43 carrier board interface. All eCAP modules are derived from the Sitara AM437x on-SoC. eCAP can be used for the following applications: ...

  • Page 46: Enhanced Pwm Module (Ehrpwm)

    Six enhanced high resolution pulse width modulator (eHRPWM) module instances are accessible through the CM-T43 carrier board interface. All eHRPWM modules are derived from the Sitara AM437x on-SoC. The ePWM modules are chained together via a clock synchronization scheme that allows them to operate as a single system when required.
  • Page 47 PWM Sync input to eHRPWM3 module or EHRPWM3_SYNCO 107* Always sync output to external PWM EHRPWM3_TRIPZONE_INPUT eHRPWM3 trip zone input Always EHRPWM3A eHRPWM3 A output. Always EHRPWM3A eHRPWM3 A output. Always Revised September 2017 CM-T43 Reference Guide...

  • Page 48: Quadrature Encoder Pulse Module (Eqep)

    For additional details on eQEP, please refer to the Sitara AM437x technical reference manual. The tables below summarize the eQEP interface signals Revised September 2017 CM-T43 Reference Guide...
  • Page 49 NOTE: Pins denoted with "*" are multifunctional. For additional details please refer to chapter of this document NOTE: Pins denoted with "^" must not be pulled or driven by carrier board during SoM power-up / reset. Revised September 2017 CM-T43 Reference Guide...

  • Page 50: Pru-Icss

    Peripheral Interfaces 4.21 PRU-ICSS The following interfaces are a part of the PRU-ICSS block of CM-T43 Please refer to chapter this document for additional details on PRU-ICSS 4.21.1 PRU-ICSS MII CM-T43 supports industrial protocols such as EtherCAT and can operate as an EtherCAT slave device.
  • Page 51 Without "E2" With "C1000M" PR1_MII1_RXD1 MII Receive Data bit 1 (MUXED) Without "E2" With "C1000M" PR1_MII1_RXD2 MII Receive Data bit 2 (MUXED) Without "E2" With "C1000M" PR1_MII1_RXD3 MII Receive Data bit 3 (MUXED) Without "E2" Revised September 2017 CM-T43 Reference Guide...

  • Page 52: Pru-Icss Uart

    4.21.3 PRU-ICSS Industrial Ethernet Peripheral CM-T43 carrier board interface features one instance of the PRU-ICSS integrated “industial ethernet peripheral” (IEP) interface. The IEP performs hardware work required for industrial ethernet functions. The IEP module features an industrial ethernet timer with 16 compare events and a digital I/O port (DIGIO).

  • Page 53: Pru-Icss Industrial Capture Interface (Pru-Icss1 Ecap)

    / reset. 4.21.4 PRU-ICSS Industrial Capture interface (PRU-ICSS1 eCAP) A PRU-ICSS eCAP module is available with CM-T43. The PRU ECAP module within the PRU- ICSS is identical to the eCAP module described in chapter 4.18 above. For additional details on PRU- ICSS IEP, please refer to the Sitara AM437x technical reference manual.

  • Page 54: Pru-Icss Gpi / Gpo

    4.21.5 PRU-ICSS GPI / GPO CM-T43 features PRU-ICSS dedicated general purpose input / output signals. This functionality is derived from the PRU-ICSS Enhanced GPIO submodule integrated within the Sitara AM437x. For additional details on PRU-ICSS GPI/GPO signals, please refer to the Sitara AM437x technical reference manual.
  • Page 55 PRU-ICSS1 PRU0 Data In Capture Enable Always Without "N4G" Without PR1_PRU0_GPI16 133* PRU-ICSS1 PRU0 Data In Capture Enable "N16G" Without "N32G" PR1_PRU0_GPI16 194* PRU-ICSS1 PRU0 Data In Capture Enable Always PR1_PRU0_GPI2 110*^ I; PD PRU-ICSS1 PRU0 Data In Always Revised September 2017 CM-T43 Reference Guide...
  • Page 56 NOTE: Pins denoted with "*" are multifunctional. For additional details please refer to chapter of this document NOTE: Pins denoted with "^" must not be pulled or driven by carrier board during SoM power-up / reset. Revised September 2017 CM-T43 Reference Guide...

  • Page 57: Timers

    4.23 General Purpose Clocks CM-T43 features two software controlled general purpose clock outputs. A carrier board designer can use these clocks for carrier board devices. For additional details on CLKOUT signals, please refer to the Sitara AM437x technical reference manual. The table below summarizes the general purpose...

  • Page 58: External Dma/Interrupt Requests

    The following signals allow carrier board components to issue DMA/Interrupt requests the Sitara AM437x SoC onboard CM-T43. For additional details on these signals please refer to the Sitara AM437x technical reference manual. The table below summarizes the external DMA interface...

  • Page 59: System Logic

    Cold reset is a non-blockable reset input to the Sitara AM437x SoC, which triggers a full logic reset to CM-T43. Cold reset is a global reset that affects every module on the device. The cold reset assertion also causes SYS_nRESWARM assertion.

  • Page 60: Boot Sequence

    Always through 10KΩ onboard CM-T43 PU33 Boot Sequence CM-T43 boot sequence defines which interface/media is used by CM-T43 to load and execute the initial software (such as U-boot). CM-T43 can load initial software from the following interfaces/media:  The on-board primary storage device (SPI Flash with pre-flashed boot-loader).

  • Page 61: Signal Multiplexing Characteristics

    Signal Multiplexing Characteristics Up to 145 of the CM-T43 carrier board interface pins are multifunctional. Multifunctional pins enable extensive functional flexibility of the CM-T43 CoM/SoM by allowing usage of a single carrier board interface pin for one of several functions. Up-to 10 functions (MUX modes) are accessible through each multifunctional carrier board interface pin.
  • Page 62 CAM0_DATA0 CAM1_DATA9 I2C1_SDA PR0_PRU1_GPO16 PR0_PRU1_GPI16 EHRPWM0_SYNCO GPIO5_19 Always DSS_DATA2 GPMC_A2 PR1_MII0_TXD3 EHRPWM2_TRIPZONE_INPUT PR1_PRU0_GPO2 PR1_PRU0_GPI2 GPIO2_8 Always MCASP0_FSR EQEP0B_IN MCASP0_AXR3 MCASP1_FSX EMU2 PR0_PRU0_GPO5 PR0_PRU0_GPI5 GPIO3_19 GPIO0_19 Always DSS_DATA3 GPMC_A3 PR1_MII0_TXD2 EHRPWM0_SYNCO PR1_PRU0_GPO3 PR1_PRU0_GPI3 GPIO2_9 Always Revised September 2017 CM-T43 Reference Guide...
  • Page 63 PR0_PRU0_GPI2 GPIO3_16 Without "A" MCASP0_ACLKR EQEP0A_IN MCASP0_AXR2 MCASP1_ACLKX MMC0_SDWP PR0_PRU0_GPO4 PR0_PRU0_GPI4 GPIO3_18 GPIO0_18 Always MCASP0_ACLKX EHRPWM0A SPI0_CS3 SPI1_SCLK MMC0_SDCD PR0_PRU0_GPO0 PR0_PRU0_GPI0 GPIO3_14 Without "A" MCASP0_FSX EHRPWM0B SPI1_CS2 SPI1_D0 MMC1_SDCD PR0_PRU0_GPO1 PR0_PRU0_GPI1 GPIO3_15 Without "A" Revised September 2017 CM-T43 Reference Guide...
  • Page 64 Pin # MODE0 MODE1 MODE2 MODE3 MODE4 MODE5 MODE6 MODE7 MODE8 MODE9 Availability GPMC_CSN3 GPMC_WAIT0 QSPI_CLK MMC2_CMD PR1_MII0_CRS PR1_MDIO_DATA EMU4 GPIO2_0 GMII2_CRS RMII2_CRS_DV Always MCASP0_AXR1 EQEP0_INDEX MCASP1_AXR0 EMU3 PR0_PRU0_GPO6 PR0_PRU0_GPI6 GPIO3_20 GPIO0_2 Without "A" Revised September 2017 CM-T43 Reference Guide...

  • Page 65: Flash Write-Protection

    The EEPROM_WP signal can be used to prevent accidental corruption of the data stored on the onboard SPI Flash as well as the onboard ID EEPROM. The CM-T43 on-board EEPROM is used to store board specific production information while the onboard SPI flash is used to store the boot-loader as described in chapter 3.4.2.

  • Page 66: Carrier Board Interface

    Carrier board Interface CARRIER BOARD INTERFACE The CM-T43 CoM/SoM carrier board interface uses the SODIMM-204 edge connector. The SoM pinout is detailed in the table below. Connector Pinout Table 68 Connector P1 Pin # CM-T43 Signal Name Ref. Pin # CM-T43 Signal Name Ref.
  • Page 67 Carrier board Interface Pin # CM-T43 Signal Name Ref. Pin # CM-T43 Signal Name Ref. UART1_RTSN 4.10 MCASP0_AXR1 I2C2_SCL 4.11 ETH1_MDI2N SPI1_CS1 4.12 MMC0_DAT4 DCAN0_RX 4.14 MMC1_DAT3 GPIO0_13 4.17 UART1_RIN 4.10 PR1_UART0_RTS_N 4.21.2 UART3_TXD 4.10 PR1_EDC_LATCH1_IN 4.21.3 GPIO0_11 4.17 TIMER5 4.22...
  • Page 68 Carrier board Interface Pin # CM-T43 Signal Name Ref. Pin # CM-T43 Signal Name Ref. GPMC_CLK GPMC_A22 GPMC_WAIT1 GPMC_A6 MCASP0_FSR ETH2_LED1 MMC2_CLK MMC2_DAT4 GPIO0_4 4.17 GPIO1_22 4.17 GPIO2_1 4.17 EQEP1_INDEX 4.20 PR1_MDIO_MDCLK 4.21.1 PR1_MII_MT1_CLK 4.21.1 PR1_MII1_CRS 4.21.1 GPMC_A5 GPMC_BE0N_CLE GPMC_A11 SPI1_CS3 4.12...
  • Page 69 Carrier board Interface Pin # CM-T43 Signal Name Ref. Pin # CM-T43 Signal Name Ref. MMC0_POW MCASP0_AHCLKX MMC0_SDCD MCASP1_AXR0 UART3_RXD 4.10 MMC2_DAT2 GPIO0_6 4.17 UART4_TXD 4.10 ECAP1_IN_PWM1_OUT 4.18 DCAN0_RX 4.14 EHRPWM2A 4.19 GPIO0_17 4.17 TIMER0 4.22 GPIO3_12 4.17 XDMA_EVENT_INTR2 4.24 SPI4_D0 4.12...
  • Page 70 Carrier board Interface Pin # CM-T43 Signal Name Ref. Pin # CM-T43 Signal Name Ref. CAM1_DATA7 GPMC_A22 MMC2_DAT3 MMC0_DAT1 UART1_DTRN 4.10 UART1_DTRN 4.10 UART2_RTSN 4.10 UART3_RXD 4.10 GPIO4_21 4.17 UART5_CTSN 4.10 PR1_EDIO_DATA_IN1 4.21.3 GPIO2_28 4.17 PR0_PRU1_GPI15 4.21.5 PR0_PRU0_GPI10 4.21.5 PR0_PRU1_GPO15 4.21.5...
  • Page 71 Carrier board Interface Pin # CM-T43 Signal Name Ref. Pin # CM-T43 Signal Name Ref. DSS_AC_BIAS_EN CAM1_DATA1 GPMC_A11 UART1_TXD 4.10 GPMC_A4 I2C2_SCL 4.11 GPIO2_25 4.17 SPI3_D1 4.12 PR1_EDIO_DATA_IN5 4.21.3 GPIO4_15 4.17 PR1_EDIO_DATA_OUT5 4.21.3 EHRPWM0_SYNCI 4.19 PR0_PRU1_GPI9 4.21.5 PR0_PRU1_GPO9 4.21.5 DSS_DATA0...
  • Page 72 Carrier board Interface Pin # CM-T43 Signal Name Ref. Pin # CM-T43 Signal Name Ref. DSS_DATA7 GPMC_A7 CAM0_DATA2 GPIO2_13 4.17 CAM1_DATA10 EQEP2_STROBE 4.20 MMC1_CLK PR1_EDIO_DATA_IN7 4.21.3 QSPI_CLK 4.13 PR1_EDIO_DATA_OUT7 4.21.3 GPIO4_24 4.17 PR1_PRU0_GPI7 4.21.5 PR1_PRU0_GPO7 4.21.5 DSS_DATA8 GPMC_A12 MCASP0_ACLKX UART2_CTSN 4.10...
  • Page 73 Carrier board Interface Pin # CM-T43 Signal Name Ref. Pin # CM-T43 Signal Name Ref. DSS_DATA14 GPMC_A18 MCASP1_ACLKX MCASP0_AXR1 UART2_RXD 4.10 UART5_CTSN 4.10 UART5_CTSN 4.10 UART5_RXD 4.10 I2C1_SDA 4.11 SPI3_D1 4.12 SPI1_D0 4.12 GPIO0_10 4.17 GPIO3_1 4.17 EQEP1_INDEX 4.20 PR1_MII_MR0_CLK 4.21.1...
  • Page 74 Carrier board Interface Pin # CM-T43 Signal Name Ref. Pin # CM-T43 Signal Name Ref. DSS_DATA23 GPMC_AD8 MMC1_DAT0 MMC2_DAT4 SPI3_CS1 4.12 USB1_DRVVBUS SPI3_SCLK 4.12 GPIO0_22 4.17 GPIO5_26 4.17 EHRPWM2A 4.19 PR1_MII_MT0_CLK 4.21.1 GPMC_CLK GPMC_CSN1 MMC1_CLK GPIO1_30 4.17 ADC1_AIN2 4.15 PR1_EDIO_DATA_IN6 4.21.3...

  • Page 75: Mating Connectors

    Carrier board Interface Pin # CM-T43 Signal Name Ref. Pin # CM-T43 Signal Name Ref. RLINEIN MCASP0_ACLKR MCASP0_AXR0 MCASP0_AXR2 MMC2_SDCD MCASP1_ACLKX SPI1_CS3 4.12 MMC0_SDWP SPI1_D1 4.12 GPIO0_18 4.17 GPIO3_16 4.17 GPIO3_18 4.17 EHRPWM0_TRIPZONE_INPUT 4.19 EQEP0A_IN 4.20 PR0_PRU0_GPI2 4.21.5 PR0_PRU0_GPI4 4.21.5 PR0_PRU0_GPO2 4.21.5...

  • Page 76: Mechanical Drawings

    Carrier board Interface Mechanical Drawings Figure 3 CM-T43 Top Revised September 2017 CM-T43 Reference Guide...

  • Page 77: Standoffs/Spacers

    Standoffs/Spacers CM-T43 has two mounting holes to physically secure the CoM/SoM to the carrier board. Secure CM-T43 to the carrier board by mounting two spacers with any adequate screws and nuts. Spacers must comply with the following specification: ...

  • Page 78: Operational Characteristics

    ±2kV Human Body Model (HBM), per ANSI/ESDA/JEDEC JS001 ±0.5kV Charged Device Model (CDM) per JESD22-C101 Ethernet ±2kV Electrostatic discharge tolerance - Human Body Model Operating Temperature Ranges The CM-T43 is available with three options of operating temperature range. Table 74 CM-T43 Temperature Range Options Range Temp.

  • Page 79: Application Notes

    It is recommended to connect the standoff holes of the carrier board to GND, in order to improve EMC.  Except for a power connection, no other connection is mandatory for CM-T43 operation. All power-up circuitry and all required pullups/pulldowns are available onboard CM-T43. ...

  • Page 80: Ethernet Magnetics Implementation

     Improper functioning of a customer carrier board can accidentally delete boot-up code from CM-T43, or even damage the module hardware permanently. Before every new attempt of activation, check that your module is still functional with CompuLab SB-SOM- T43 carrier board.

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