Denon DRA-F107 Service Manual page 30

detected zero-crossing to the switch-on of the main
switch t , theoretically:
delay
T
osc
t = --------- - t –
delay
4
This time delay should be matched by adjusting the
time constant of the RC network which is calculated as:
R R
zc1 zc2
= C --------------------------- -
td zc
R + R
zc1 zc2
3.3.1.3 Switch-on Determination
In the system, turn-on of the power switch depends on
the value of the up/down counter, the value of the zero-
crossing counter and the voltage at the ZC pin v
Turn-on happens only when the value in the both
counters are the same and the voltage at the ZC is
lower than the threshold V
values from both counters, a digital comparator is used.
Once these counters have the same value, the
comparator generates a signal which sets the on/off
flip-flop, only when the voltage v
threshold V .
ZCT1
Another signal which may trigger the digital comparator
is the output of a T clock signal, which limits the
sMax
maximum off time to avoid the low-frequency
operation.
During active burst mode operation, the digital
comparator is disabled and no pulse will be generated.
1
0 .8
0 .6
0 .4
0 .2
0
0 5
Figure 5 Maximum current limit versus MOSFET maximum on time
[3]
[4]
ZC
. For comparison of the
ZCT1
is lower than the
ZC
10
Ton(us )
DRA-F107 / DRA-F107DAB
3.3.2 Switch-off Determination
In the converter system, the primary current is sensed
by an external shunt resistor, which is connected
between low-side terminal of the main power switch
and the common ground. The sensed voltage across
the shunt resistor v
CS
measurement unit, and its output voltage v
compared with the regulation voltage v
voltage v exceeds the voltage v
1
is reset. As a result, the main power switch is switched
off. The relationship between the v
described by:
v = 3.3 v + 0.7
1 CS
To avoid mistriggering caused by the voltage spike
.
across the shunt resistor after switch-on of the main
power switch, a 330ns leading edge blanking time
applies to output of the comparator.
3.3.3 Foldback Point Correction
In addition to the cycle-by-cylce primary current
limitation, the IC incorporats a foldback point
correction. The current limit on CS pin voltage is now a
time dependent one. If the mains input voltage is high,
the MOSFET on time will be short and the current limit
will be low. In such a way, the maximum output power
for the SMPS designed with ICE2QS01 will be nearly
constant against the variations of mains input voltage.
The current sense voltage limit versus the MOSFET
maximum on time is shown in Figure 5.
15 20
30
Functional Description
is applied to an internal current
. Once the
reg
, the output flip-flop
REG
and the v
1
2 5 30
is
1
is
cs
[5]