Denon DRA-F107 Service Manual page 20

SEMICONDUCTORS
Only major semiconductors are shown, general semiconductors etc. are omitted to list.
The semiconductor which described a detailed drawing in a schematic diagram are omitted to list.
1. IC's
M3062LFGPGP (IC62)
M3062LFGPGP Terminal Function
Pin Port Port
No. Function setting
1 P94 O
2 P93 O
3 TB2IN I
4 P91 O
5 TB0IN I
6 BYTE
7 CNVSS I
8 P87 O
9 P86 O
10 RESET I
11 XOUT
12 VSS
13 XIN
14 VCC
15 NMI I
16 P84 O
17 INT1 INT
18 INT0 INT
19 P81 I
20 P80 I
21 TA3IN I
22 TA3OUT I
23 P75 O
24 P74 O
25 P73 O
26 CLK2 O
27 RXD2 I
75
76
100
1
Port Name
[LED_RL] [STANDBY Red LED output. ON:High]
FL RESET Reset output to FLD
FUNC_JOGB FUNCTION encoder Pulse-B input
Not Used:N.C.
FUNC_JOGA FUNCTION encoder Pulse-A input
(VSS) GND
FLASH CNVss Select input of Flash rom write mode
Not Used:N.C.
Not Used:N.C.
RESET Reset input
XTAL(16MHz) Xtal output
(VSS) GND
XTAL(16MHz) Xtal input
(VCC) Positive power
(PullUp) Pull up
Not Used:N.C.
POWER KEY Power button input (interrupt input)
/DBRXD DENON BUS Data input (interrupt input)
50/60 50Hz/60Hz AC Input
H/P SW HEAD PHONE insert detect signal input
VOL JOGB VOL encoder Pulse-B input
VOL JOGA VOL encoder Pulse-A input
FLCS Chip Select output to FLD
LED G POWER/SANDBY Green LED output. ON:High
LED R POWER/SANDBY Red LED output. ON:High
/DBCLK(DENON BUS) Serial Clock output for DENON BUS
/DBRXD(DENON BUS) Serial Data input for DENON BUS
DRA-F107 / DRA-F107DAB
51
50
26
25
Explaanation
20
Output of
Standby &
Default
L
L
HI-Z
L
HI-Z
-
HI-Z
L
L
HI-Z
-
-
-
-
HI-Z
L
HI-Z
HI-Z
HI-Z
HI-Z
HI-Z
HI-Z
L
L
L
H
HI-Z