HP 85662A Troubleshooting And Repair Manual page 221

IF-DI S P L A Y S E C T I O N
1
A3A6 MAIN CONTROL
8 5 6 6 2 - 6 0 1 4 6
(SERIAL PREFIX: 2 4 0 3 A )
PIN
1
19
2
20
3
21
4
22
5
23
6
24
7
25
8
26
9
27
10
28
11
29
12
30
13
31
14
32
15
33
16
34
17
35
18
36
S1GNAL
BRIGHT
FS
LLG BLANK
BLINK
DIM
CHAR
NC
LROM EN
CE
INSEL A
INSEL B
DOT EN
HOLD
PS3
QS/B
PS2
QS1
PS1
QS2
PS/
QS3
IOC
RS EN
NC
LTON
NC
LQ
NC
LCLRSA
NC
RSHS
NC
INCRSA
LTST B
LRSTO
LTST A
TO/FROM
A3A2P2-22
A3A2P2-23
A3A2P2-24
A3A2P2-25
A3A2P2-26
A3A3P2-1
A3A4P1-20
A3A4P1-22
A3A9P1-13
A3A9P1-12
A3A2P2-20
A3A8P1-27,
A3A9P1-15
A3A7P1-29
A3A7P1-30
A3A7P1-11
A3A7P1-31
A3A7P1-12
A3A7P1-32
A3A7P1-13
A3A7P1-33
A3A7P1-14
A3A9P1-30
A3A7P1-15
A3A7P1-16
A3A4P1-2
A3A1P1-20
A3A4P1-21
A3A7P2-4
A3A2P1-18
A3A7P2-22
FUNCTION
BLOCK
L
L
L
L
L
L
L
J
L
L
L
L
E
B
E
B
E
B
E
B
E
6
C
F
G
6
G
L
G
L
P2
PIN
1
19
2
20
3
21
4
22
5
23
6
24
7
25
8
26
9
27
10
28
11
29
12
30
13
31
14
32
15
33
16
34
17
35
18
36
SIGNAL
KS1
CLK
K$0
LCLK
KS3
BS
KS2
LWRITE
RM2
LRTN
F3
INTR
F1
RM1
F2
RMjB
LDMEN
B1
B2
B3
B4
B5
B6
B7
B8
NC
B10
B11
DGND
DGND
+5V
DGND
+6V
NC
TO/FROM
A3A5P1-19
A3A7A2-6
A3A5P1-1
A3A7P2-24
A3A5P1-20
A3A5P1-3
A3ASP1-2
A3A4P1-19
A3A5P1-21
A3A7P2-26
A3A5P1-23
A3A2P2-28
A3A5P1-24
A3A5P1-4
A3A5P1-25
A3A5P1-5
A3A5P1-27
A3A5P1-6
- »
j
>
. DIGITAL
f STORAGE
BUS
FUNCTION
BLOCK
K
L
K
G
K
F
K
E
B
F
B
F
B
B
B
B
B
B
H
NC
NC
L
L
NC
L
H
NC
NC
NC
M
M
M
M
M
N O T E S :
NSEL A
P1-6 INSEL B
P1-24 DOT EN
P1-7 HOLD
REFERENCE DESIGNATORS WITHIN
THIS ASSEMBLY ARE ABBREVIATED.
FOR COMPLETE REFERENCE DESIG-
NATI ON,PREFIX ABBREVIATION WITH
ASSEMBLY DESIGNATION.
UNLESS OTHERWISE INDICATED:
RESISTANCE IS IN OHMS (ft)
CAPACITANCE IS IN MICROFARADS^uF )
INDUCTANCE IS IN MICROHENRIES(^H )
UNLESS OTHERWISE INDICATED:
LOGIC LEVELS ARE TTL:
+2.0V TO +5.0V=L0GIC'1' =HIGH
OV TO +0.8V-L0GIC '0' -LOW
ROMS U4-U11 ARE USED IN PAIRS. U4.U6,
U9, AND U11 ARE THE MAIN PROGRAM. ROMS
U5.U7.U8, AND U10 ARE TEST PROGRAM
ROMS. ALL CONNECT IONS TO EACH PAIR
U4/U5, U6/U7, U8/U9, AND U11/U10ARE
THE SAME EXCEPT FOR PIN 15 AND PIN 2<
20.
U4.U6.U9.U11
U5.U7.U8.U10
PIN 15
TP6
GND
PIN 20
+5V
TP6
TO ENABLE THE TEST PROGRAM. CONNECT
TP3 TO TP6.
5. U3 PIN CONFIGURATION:
U3 (4700Q)
R1 £ R 2 | R3S R 4 * R55 R6S R7
T T 2 13 P4
6. MNEMONIC TABLE:
MNEMONIC
Bft1 GUT
FS
LLG BLANK
BLINK
DIM
CHAR
LROM EN
CE
INSEL A
INSEL B
DOT EN
HOLD
PS/-PS3
QS/J-QS3
IOC
RSEN
LTON
LQ
LCLRSA
RSHS
1NCRSA
LTSTA
LTSTB
LRSTO
KS/-KS3
CLK
LCLK
BS
LDMEN
LWRITE
RM0-RM2
LRTN
F/>-F3
INTR
B/-B11
DESCRIPTION
BRIGHT CRT DISPLAY
CONTROL
FAST SWEEP MODE
LOW-LINE GENERATOR
BLANK IMG CONTROL
BLINK CRT DI SPLAY
CONTROL
DIM CRT D I SPLAY CONTROL
CHARACTER MODE DI SPLAY
CONTROL
LOW-ROM ENABLE
MEMORY CHIP ENABLE
INPUT SELECT BIT A
INPUT SELECT B
DOT ENABLE
TRACK AND HOLD CONTROL
I/O POTR SELECTION
BITS ,0-3
QUALIFIER SELECTION
BITSjB-3
I/O PORT INPUT/OUTPUT
CONTROL
RESET PEAK DETECTORS
ENABLE
LOW-TURN ON
LOW-SELECTED QUALIFIER
LOW-CLEAR STROKE ADDRESS
RESET HIGH SWEEP
INCREMENT STROKE ADDRESS
LOW-INPUT TEST A DATA
LOW-INPUT TEST B DATA
LOW-RESET TRIGGER
CONSTANT SELECT I ON
BITS J9-3
8MHz SYSTEM CLOCK
I VERTED CLOCK
BLOCK SWITCH CONTROL
LOW-DATA MANIPULATOR
OUTPUT ENABLE
MEMORY WRITE CONTROL
RAM REGISTER SELECTION
BITS/J-2
LOW-ENABLE INTERRUPT
RETURN
PART OF FUNCTION
SELECT I ON BITS £-2
INTERUPT CONTROL
DIGITAL STORAGE BUS
DATA BI TS Jtf-11
7. UNLESS OTHERWISE INDICATED:
SIGNALS ENTER AT LEFT SIDE AND EXIT AT
RIGHT SIDE OF FUNCTION BLOCKS.
A 3 A 6
A 3 A 6 MAIN C O N T R O L . S C H E M A T I C DIAGRAM