Denon AVR-4802 Service Manual page 15
Av surround receiver/amplifier
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Also See for AVR-4802:
- Operating instructions manual (72 pages) ,
- Brochure & specs (2 pages) ,
- Control protocol (11 pages)
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TMP95FY64F (IC801)
7 5
7 6
1 0 0
1
TMP95FY64F Terminal Function
Pin.
Name
Symbol
I/O Type Det Op Res
No.
1
VREFL
VREFL
2
AVss
AVss
3
AVcc
AVcc
4
DAOUT0
DAOUT0
5
DAOUT1
DAOUT1
O
C
Od
6
_NMI
_NMI
I
7
P53/_BUSRQ
ASIC RESET
O
N
Eu
8
P54/_BUSAK
WP1
O
C
Od
9
P55/_WAIT
WP2
O
C
Od
10
P56/INT0
B.DOWN
I
E↓&L
Eu
11
P57/SCLK2/_CTS2
ROM_RES1
O
C
Od
12
P80/TxD0
MISO
O
C
13
P81/RxD0
MOSI
I
14
P82/SCLK0/_CTS0
CLK
I/O
C
15
P83/TxD1
DIR MOSI
O
C
16
P84/RxD1
DIR MISO
I
Lv
17
P85/SCLK1/_CTS1
DIR CLK
O
C
18
P86/TxD2
TxD
O
C
19
P87/RxD2
RxD
I
Lv
20
P60/_CS0
D.EXP OE
O
C
21
P61/_CS1
D.EXP CLK
O
C
22
P62/_CS2
D.EXP DATA
O
C
23
P63/_CS3
D.EXP STB
O
C
24
CLK
CLK
O
C
Eu
25
Vcc
Vcc
26
Vss
I/O1
27
X1
Xin
I
28
X2
Xout
O
29
_EA
_EA
30
_RESET
RESET
I
Lv
Eu
31
P70/TI0/INT1
DSP ACK1
I
E↑&L
32
P71/TO1
_DSP1 RESET
O
C
Od
33
P72/TO3/INT2
AC-3 RF DET.
I
E↓&L
34
P73/TI4/INT3
DAC-192
O
C
35
P74/TO5
_DSP2 RESET
O
C
Od
36
P75/TO7/INT4
_REQ
O
C
Eu
37
P90/TI8/INT5
_ACK
I
E↓&L
Eu
38
P91/TI9/INT6
CSI
I
Lv
39
P92/TO8
EMP
I
Lv
40
P93/TO9
DEEPM
O
C
Ed
41
P94/TIA/INT7
_CS
I
E↑&L
Od
42
P95/TIB/INT8
ERR
I
E↑&L
43
P96/TOA/TOB
DIR RESET
O
C
44
Vcc
Vcc
45
P00/D0
DIT_RESET
C
46
P01/D1
DIT CLK
C
47
P02/D2
DIT uDATA
C
48
P03/D3
DIT ST
C
49
P04/D4
DIT_CS
C
50
P05/D5
DIT R/W
C
51
P06/D6
DH/RESET
C
5 1
5 0
2 6
2 5
Ini
Function
A/D ref. GND
A/D GND
AD +5V
No connection
L
L
No connection
Not used (fixed to H)
H
H
ASIC control terminal (L: Reset)
Memory write protect for DSP1
Memory write protect for DSP2
Z
Power down detect (L: Detected)
Memory reset for DSP1
MAIN-SUB µcom comm. control terminal (Data out)
MAIN-SUB µcom comm. control terminal (Data in)
MAIN-SUB µcom comm. control terminal (I2C clock in/out)
Z
L
DIR control terminal (LC89055Q), control data output
DIR control input terminal (LC89055Q), control data input
Z
L
DIR control terminal (LC89055Q), control clock output
Z
L
Data send output to external (common with 1394 data comm.)
Data receive input from external (common with 1394 data comm.)
Z
L
Port Expander control out for DIGITAL input switching (TC4094B)
Z
L
Port Expander control out for DIGITAL input switching (TC4094B)
Z
L
Port Expander control out for DIGITAL input switching (TC4094B)
Z
L
Port Expander control out for DIGITAL input switching (TC4094B)
+5V
GND
X'tal connection
X'tal connection
Fixed to +5V
L
Reset input
DSP1 host interface comm. respond input (L: OK)
L
L
DSP1 reset output terminal (L: Reset)
AC-3 RF signal detect input (L: AC-3 RF signal input)
Sets D/A to 192k
L
L
DSP2 reset output terminal (L: Reset)
MAIN-SUB µcom comm. control terminal (L: Comm. request from SUB)
H
L
MAIN-SUB µcom comm. control terminal (L: Ack. return from MAIN)
DIR control input terminal (LC89055Q), L: PCM
H: EMP ON
L
L
DIR control input terminal (LC89055Q), L→H: Cannel status change
DIR control input terminal (LC89055Q), H: ERR
Z
L
DIR control input terminal (LC89055Q), L: Reset
+5V
Z
L
DIT control terminal
Z
L
DIT control terminal
Z
L
DIT control terminal
Z
L
DIT control terminal
Z
L
DIT control terminal
Z
L
DIT control terminal
Z
L
DHIVA board reset (fixed to L)
Pin.
Name
Symbol
I/O Type Det Op Res
No.
52
P07/D7
DMUTE
C
53
P10/D8
I/O1
I/O
C
54
P11/D9
I/O2
I/O
C
55
P12/D10
I/O3
I/O
C
56
P13/D11
I/O4
I/O
C
57
P14/D12
I/O5
I/O
C
58
P15/D13
I/O6
I/O
C
59
P16/D14
I/O7
I/O
C
60
P17/D15
I/O8
I/O
C
61
AM8/_16
62
Vss
Vss
63
Vcc
Vcc
64
P27/A23
_DSP REQUEST1
O
C
65
P26/A22
WRITE1
O
C
66
P25/A21
_DSP REQUEST2
O
C
67
P24/A20
WRITE2
O
C
68
P23/A19
DSP ACK2
I
E↑&L
69
P22/A18
BUSY2
I
Lv
70
P21/A17
FLAG 3A
I
Lv
71
P20/A16
BUSY1
I
Lv
72
P37/A15
SEL CK
O
C
73
P36/A14
DIR CE
O
C
74
P35/A13
FLAG 3B
I
Lv
75
P34/A12
DAC-RESET2
O
C
Od
76
P33/A11
DIGITAL POWER
O
C
77
P32/A10
DIR AUTO
O
C
Od
78
P31/A9
BPSYNC
O
C
79
P30/_B00T/A8
_B00T
I
Lv
Eu
80
P47/A7
_DEMOD RESET
O
C
Od
81
P46/A6
DEMOD ON
O
C
Od
82
P45/A5
FGAIN
O
C
83
P44/A4
A/D RESET
O
N
Eu
84
P43/A3
DAC-RESET1
O
C
Od
85
P42/A2
DAC-DIF.
86
P41/A1
DIG. (AC3) MUTE
O
C
Od
87
P40/A0
ERR MUTE_
O
C
Od
88
P50/_RD
DH IN
O
C
89
P51/_WR
DH OUT
O
C
90
P52/_HWR
ROM_RES2
O
C
Od
91
Vss
Vss
92
PA0/AN0
96K DET
I
Lv
93
PA1/AN1
DHERR
I
Lv
94
PA2/AN2
I
Lv
95
PA3/AN3/_ADTRG
96
PA4/AN4
I
Lv
97
PA5/AN5
I
Lv
98
PA6/AN6
I
Lv
99
PA7/AN7
MODE-0-SUB
I
Lv
100
VREFH
VREFH
Note:
Pin No.
: Terminal number of microcomputer.
Port Name
: The name entered in the data sheet of microcomputer.
Symbol
: Symbolized interface function.
I/O
: Input or out of part.
"I"
= Input port
"O"
= Output port
Type
: Composition of port in case of output port.
"C"
= CMOS output
"N"
= NMOS open drain output
"P"
= PMOS open drain output
Op
: Pull up/Pull down selection information.
"Iu"
= Inner microcomputer pull up
"Id"
= Inner microcomputer pull down
"Eu" = External microcomputer pull up
"Ed" = External microcomputer pull down
Det
: Indicates judging state of input port. Level detection is "LV"; Edge detection is "Ed"; Detection by both shifting is "E&L"; Serial data
detection is "S" (Serial data output is also "S").
Res
: State at reset.
"H"
= Outputs High Level at reset
"L"
= Outputs Low Level at reset
"Z"
= Becomes High impedance mode at reset
Ini
: Initial output state.
Function
: Function and logical level explanation of signals to be interface.
AVR-4802/AVC-A11SR
Ini
Function
Z
L
Digital input MUTE control output (same control as SELCK)
Z
L
DSP comm. terminal (ADSP21061L:D16)
Z
L
DSP comm. terminal (ADSP21061L:D17)
Z
L
DSP comm. terminal (ADSP21061L:D18)
Z
L
DSP comm. terminal (ADSP21061L:D19)
Z
L
DSP comm. terminal (ADSP21061L:D20)
Z
L
DSP comm. terminal (ADSP21061L:D21)
Z
L
DSP comm. terminal (ADSP21061L:D22)
Z
L
DSP comm. terminal (ADSP21061L:D23)
Fixed to +5V
GND
+5V
Z
L
DSP1 (ADSP21061L-A:IRQ 1_) host interface interrupt req. output, L: REQ
Z
L
DSP1 comm. control terminal (H: DATA WRITE)
Z
L
DSP2 (ADSP21061L-A:IRQ 1_) host interface interrupt req. output, L: REQ
Z
L
DSP2 comm. control terminal (H: DATA WRITE)
DSP2 host interface comm. respond input (L: OK)
DSP busy check flag (ADSP21061L-B:FLAG 2B) input, L: Normal
Special flag for ROM update (ADSP21061L-A:FLAG 3A)
DSP busy check flag (ADSP21061L-A:FLAG 2A) input, L: Normal
Z
L
ADC/DIR data/clock switching control terminal (L: ADC)
Z
L
DIR control terminal (LC89055Q), control chip enable output
Special flag for ROM update (ADSP21061L-A:FLAG 3B)
L
H
DAC control terminal (L: Power down, ↑ : Reset, H: Normal)
Z
L
DIGITAL power ON/OFF switching
Z
L
Z
L
Z
Single Chip/Single Boot switching input (H & Reset: Single Chip Mode)
L
L
Demodulator reset output (L: Reset)
L
L
Demodulator osc. control output (H: Osc.)
Z
L
IV AMP GAIN switching control output (L: Sub-woofer on)
H
H
A/D control terminal (L: Reset)
DAC control terminal (L: Power down, ↑ : Reset, H: Normal)
L
H
DAC differential use: H
Z
L
Digital mute control output (L: AC-3 or DTS decode possible)
L
L
Pop noise preventive mute control output
Z
L
For 1394 (fixed to L)
Z
L
For 1394 (fixed to L)
Memory reset for DSP2
GND
96k signal detect input, H: 96k
DHIVA board error input (fixed to L)
Not used (Pull down)
Not used (Pull down)
Not used (Pull down)
Not used (Pull down)
Not used (Pull down)
FLASH ROM rewrite mode input
AD ref. +5V
15
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