Reset Circuitry - Heathkit HD-1410 Instruction Manual

NEXT-BIT MEMORIES (NBM)
There are two "next-bit memories;" one for dots, composed of gates IC1A and IC2A and one for
dashes, composed of gates IC1B and IC2B. Each pair of gates is cross-coupled to form an R-S
(set-reset) flip-flop. Since their operation is similar, only the dash NBM will be discussed.
Figure 10
When no bit is being sent, 1C2 pin 8 is high since the clock is tow. The dash NBM is in the reset
condition, with IC2 pin 6 high and IC1 pin 3 low. This low is applied to 1C3 pin 4. Therefore, IC3
pin 6 is high. (Similarly, IC3 pin 8 is also high.) When the dash paddle is keyed, IC1 pin 1 is
grounded momentarily through the paddle contacts. This causes IC1 pin 3 to go high. IC2 pins 4
and 5 are both high, so IC2 pin 6 goes low. This low is applied to IC1 pin 2 and holds IC1 pin 3
high after the paddle is released. IC3B now has a high on all three inputs, so pin 6 is low. This low
is applied to IC1 pin 13, and IC1 pin 11 goes high. IC1 pin 8 goes low, and the bit generator be-
gins to form a dash (since IC4 pin 2 is high).
PRESENT-BIT MEMORY (PBM)
Note that IC3A and B form an R-S flip-flop which, depending on its state, causes the bit generator
to form dots or dashes äs described in the section on the bit generator.

RESET CIRCUITRY

At the end of a bit, whether dot or dash, the PBM must assume the state of the next bit to be
sent. This is accomplished by the reset circuitry. IC5B, IC20, resistor R3 and capacitor C1 form the
dash reset circuit. (The dot reset circuitry is composed of IC5A, IC2C, resistor R4, and capacitor C2
operates the same). Iambic operation requires that if both paddles are closed, or if the dot paddle
is keyed during a dash bit, or the dash paddle is keyed during a dot bit, the next bit must be oppo-
site to that being sent.
Assume a dot is being sent. This means that IC3 pin 8 is low and IC3 pin 6 is high. This high is ap-
plied to IC5 pin 9 and holds IC5 pin 10 low. The trailing edge of the clock pulse occurring at the
end of the dot bit mark takes IC3 pin 12 low. At this time, IC5A has both inputs low, and IC5 pin
13 goes high. This enables IC2C for the next clock pulse, which occurs at the end of the dot bit.